User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 452
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
iTD DWords 1 to 8: Transaction Status and Control List
DWords 1 through 8 are transaction control and status. Each transaction description includes:
• Status results field
• Transaction length (bytes to send for OUT transactions and bytes received for IN transactions)
• Buffer offset. The PG and Transaction x Offset fields are used with the buffer pointer list to
construct the starting buffer address for the transaction
The host controller uses the information in each transaction description plus the endpoint
information contained in the first three DWords of the Buffer Page Pointer list, to execute a
transaction on the USB.
2:1 Transaction Descriptor Type, TYP. Set to 00 (iTD type). Refer to section 15.12.2 Transfer Descriptor
Type (TYP) Field for general information.
0 Terminate transfer, T.
• 0: link to the Next iTD Pointer field; the address is valid.
• 1: end the transaction, the Next iTD Pointer field is not valid.
Table 15-27: USB Host iTD Dwords 1 to 8: Transaction Status and Control List
Bits Description
31:28 Status:
Active Status [31]. Set to 1 by the HCD to enable the execution of an isochronous transaction. When
the transaction associated with this descriptor is completed, the host controller sets this bit to 0
indicating that a transaction for this element should not be executed when it is next encountered in
the schedule.
Data Buffer Error Status [30]. Set to a 1 by the host controller during status update to indicate that
the host controller is unable to keep up with the reception of incoming data (overrun) or is unable to
supply data fast enough during transmission (under run). If an overrun condition occurs, no action is
necessary.
Babble Detected Status [29]. Set to 1 by the host controller during status update when 'babble' is
detected during the transaction generated by this descriptor.
Transaction Error Status [28]. Set to 1 by the host controller during status update in the case where
the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit can
only be set for isochronous IN transactions.
27:16 Transaction {7:0} Length. For an OUT transaction, this field is the number of data bytes the host
controller will send during the transaction. The host controller is not required to update this field to
reflect the actual number of bytes transferred during the transfer.
For an IN transaction, the initial value of the field is the number of bytes the host expects the
endpoint to deliver. During the status update, the host controller writes back the field the number of
bytes successfully received.
• 000h: zero length data.
• 001h: one byte.
• 002h: two bytes.
• ...
• C00h: 3072 bytes (maximum).
Table 15-26: USB Host iTD DWord 0: Next Link Pointer (Cont’d)
Bits Description