User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 453
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
iTD DWords 9 to 15: Buffer Page Pointer List
DWords 9-15 of an isochronous transaction descriptor are nominally page pointers (4 KB aligned) to
the data buffer for this transfer descriptor. This data structure requires the associated data buffer to
be contiguous, but allows the physical memory pages to be non-contiguous. Seven page pointers
are provided to support the expression of eight isochronous transfers. The seven pointers allow for
3 (transactions) * 1,024 (maximum packet size) * 8 (transaction records) (24,576 bytes) to be moved
with this data structure, regardless of the alignment offset of the first page.
Since each pointer is a 4 KB aligned page pointer, the least significant 12 bits in several of the page
pointers are used for other purposes.
15 Interrupt On Complete, IOC. If this bit is set to 1, it specifies that when this transaction completes,
the host controller should issue an interrupt at the next interrupt threshold.
14:12 Page Select, PG. These bits are set by the HCD to indicate which of the buffer page pointers the offset
field in this slot should be concatenated to produce the starting memory address for this transaction.
The valid range of values for this field is 0 to 6.
11:0 Transaction {7:0} Offset. This field is a value that is an offset, expressed in bytes, from the beginning
of a buffer. This field is concatenated onto the buffer page pointer indicated in the adjacent PG field
to produce the starting buffer address for this transaction.
Table 15-28: USB Host iTD DWords 9 to 15: Buffer Page Pointer List
Bits Description
DWord 9
31:12 Buffer Pointer (Page 0). 4KB-aligned pointer to system memory address bits [31:12].
11:8 Endpoint Number (EndPt). Select the endpoint for the device serving as the data source or sink.
7 Reserved. Bit reserved for future use and should be initialized by the HCD to 0.
6:0 Device Address. Select the specific device serving as the data source or sink.
DWord 10
31:12 Buffer Pointer (Page 1). 4KB-aligned pointer to system memory address bits [31:12].
11 Direction (IO). Select the high-speed transaction for an IN or OUT PID.
• 0: OUT
• 1: IN
10:0 Maximum Packet Size. This directly corresponds to the maximum packet size of the associated
endpoint (wMaxPacketSize). This field is used for high-bandwidth endpoints where more than one
transaction is issued per transaction description (e.g., per microframe).
This field is used with the Multi field to support high-bandwidth pipes. This field is also used for all
IN transfers to detect packet babble. The HCD should not set a value larger than 1,024 (400h). Any
value larger yields undefined results.
DWord 11
31:12 Buffer Pointer (Page 2). 4KB-aligned pointer to system memory address bits [31:12].
11:2 Reserved. This bit reserved for future use and should be set to 0.
Table 15-27: USB Host iTD Dwords 1 to 8: Transaction Status and Control List (Cont’d)
Bits Description