User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 455
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.12.4 Split Transaction Isochronous Transfer Descriptor (siTD)
This data structure is used to manage FS isochronous transfers via split transactions to USB 2.0 Hub
Transaction Translator. There are additional fields used for addressing the hub and scheduling the
protocol transactions (for periodic).
siTD DWord 0: Next Link Pointer
DWord 0 of a siTD is a pointer to the next schedule data structure.
siTD DWords 1 and 2: Endpoint Capabilities and Characteristics
DWords 1 and 2 specify static information about the full-speed endpoint, the addressing of the
parent Companion Controller, and microframe scheduling control.
Table 15-29: USB Host Split-Transaction Isochronous Descriptor (siTD) Format
Reference Type 313029282726252423222120191817161514 13 121110 9 8 7 6 5 4 3 2 1 0 DWord
Table 15-30 Next Ptr Next Link Pointer 00 TYP T 0
Table 15-31
Endpt
Cap/Char
IO Port Number R Hub Addr
reserved
EndPt R Device Address 1
reserved Microframe C-mask Microframe S-mask 2
Table 15-32 xfer State
IOC
P reserved Total Bytes Microframe C-prog-mask Status 3
Table 15-33
Buffer
Page Ptrs
Buffer Pointer (Page 0)
Current Offset 4
Buffer Pointer (Page 1)
reserved
TP T-count 5
Table 15-34 Back Link Back Pointer 0 T 6
Host Controller Read/Write Host Controller Read-only
Table 15-30: USB Host siTD DWord 0: Next Link Pointer
Bits Description
31:5 Next Link Pointer. This field contains the address of the next data object to be processed in the
periodic list and corresponds to memory address signals [31:5], respectively.
2:1 Transaction Descriptor Type, TYP. Set to 10 (siTD type). Refer to section 15.12.2 Transfer Descriptor
Type (TYP) Field for general information.
0Terminate transfer, T.
• 0: link to the Next Link Pointer field; the address is valid.
• 1: end the transaction, the Next Link Pointer field is not valid.
Table 15-31: USB Host siTD DWords 1 and 2:Endpoint State
Bits Description
DWord 1: Endpoint and Transaction Translator Characteristics
31 Direction, IO. Encodes the FS transaction as an IN or OUT.
• 0: OUT
• 1: IN
30:24 Port Number. This field is the port number of the recipient Transaction Translator.
23 Reserved. Bit reserved and should be set to 0.
22:16 Hub Address, Hub Addr. Device address of the Companion Controller’s hub.