User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 457
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
siTD DWord 3: Transfer Status and Control
DWord 3 is used to manage the state of the split data transfer.
Status bits [7:0]
• Active Status [7]. Set to 1 by the HCD to enable the execution of an isochronous split
transaction by the Host Controller
• ERR Status [6]. Set to a 1 by the host controller when an ERR response is received from the
Companion Controller.
• Data Buffer Error Status [5]. Set to a 1 by the host controller during status update to indicate
that the host controller is unable to keep up with the reception of incoming data (overrun) or is
unable to supply data fast enough during transmission (under run). In the case of an under run,
the host controller will transmit an incorrect CRC (thus invalidating the data at the endpoint). If
an overrun condition occurs, no action is necessary.
• Babble Detected Status [4]. Set to 1 by the Host Controller during status update when 'babble'
is detected during the transaction generated by this descriptor.
• Transaction Error Status [3]. Set to 1 by the host controller during status update in the case
where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.).
This bit can only be set for isochronous IN transactions.
• Missed Microframe Status [2]. The host controller detected that a host-induced holdoff
caused the host controller to miss a required complete-split transaction.
• Split Transaction State Status [1].
- 0: Do Start Split. This value directs the host controller to issue a Start split transaction to
the endpoint when a match is encountered in the S-mask.
- 1: Do Complete Split. This value directs the host controller to issue a Complete split
transaction to the endpoint when a match is encountered in the C-mask.
• Reserved [0]. Bit reserved for future use and should be set to 0.
Table 15-32: USB Host siTD DWord 3: Transfer Status and Control
Bits Description
31 Interrupt On Complete, IOC.
• 0: Do not interrupt when transaction is complete
• 1: Do interrupt when transaction is complete
When the host controller determines that the split transaction has completed it will assert a hardware
interrupt at the next interrupt threshold.
30 Page Select, P. Used to indicate which data page pointer should be concatenated with the Current
Offset field to construct a data buffer pointer (0 selects Page 0 pointer and 1 selects Page 1). The host
controller is not required to write this field back when the siTD is retired (Active bit transitioned from
a 1 to a 0).
29:26 Reserved. Field reserved and should be set to 0.
25:16 Total Bytes To Transfer, Total Bytes. This field is initialized by the HCD to the total number of bytes
expected in this transfer. Maximum value is 1,023 (3FFh).
15:8 Microframe Complete-split Progress Mask, uFrame C prog-mask. This field is used by the host
controller to record which split-completes has been executed.
7:0 Status [7:0]. Refer to text.