User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 458
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
siTD DWords 4 and 5: Buffer Pointer List
DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one
physical page cross. The most significant 20 bits of each DWord in this section are the 4K (page)
aligned buffer pointers. The least significant 12 bits of each DWord are used as additional transfer
state.
siTD DWord 6: Back Link Pointer
DWord 6 of a siTD is simply another schedule link pointer. This pointer is either 0 or references an
siTD data structure. This pointer cannot reference any other schedule data structure.
Table 15-33: USB Host siTD DWords 4 and 5: Buffer Pointers
Bits Description
DWord 4
31:12 Buffer Pointer (Page 0). 4 KB aligned pointer to system memory address bits [31:12].
11:0 Current Offset. The 12 least significant bits of the Page 0 pointer is the current byte offset for the
current page pointer (as selected with the page select bit (P field)). The host controller is not required
to write this field back when the siTD is retired (Active bit transitioned from a 1 to a 0).
DWord 5
31:12 Buffer Pointer (Page 1). 4 KB aligned pointer to system memory address bits [31:12].
11:5 Reserved. Bit reserved for future use and should be set to 0.
4:3 Transition position, TP. This field is used with T-count to determine whether to send all, first, middle,
or last with each outbound transaction payload. The HCD must initialize this field with the
appropriate starting value. The host controller must correctly manage this state during the lifetime
of the transfer. The bit encodings are:
• 00: All. Entire FS transaction data payload is in this transaction (the payload is less than or equal
to 188 bytes.)
• 01: Begin. First data payload for a FS transaction that is greater than 188 bytes.
• 10: Mid. Middle payload for a FS OUT transaction that is greater than 188 bytes.
• 11: End. Last payload for a FS OUT transaction that was greater than 188 bytes.
2:0 Transaction count, T-Count. The HCD initializes this field with the number of OUT start-splits this
transfer requires. Any value larger than 6 is undefined.
Table 15-34: USB Host siTD DWord 6: Back Pointer
Bits Description
31:5 Back Pointer. Physical memory pointer to a siTD.
4:1 Reserved. Field reserved and should be set to 0.
0 Terminate transfer, T.
• 0: link to the Back Pointer field; the address is valid.
• 1: end the transaction, the Back Pointer field is not valid.