User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 46
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
2.4 PS–PL Voltage Level Shifter Enables
All of the signals and interfaces that go between the PS and PL traverse a voltage boundary. These
input and output signals are routed through voltage level shifters. The majority of the voltage level
shifters are enabled by the slcr.LVL_SHFTR_EN register. The voltage level shifter enables for some
PS-PL traversing signals are controlled with the PL power state. These include signals for the XADC,
PL, and EMIO JTAGs; the PCAP interface; and other modules.
The enabling and disabling of the voltage level shifters must be managed during the PL power-up
and power-down sequences to avoid extraneous logic level transitions on the input signals to the PS
modules. Disable the voltage level shifters before the PL is powered down. Similarly, enable the level
shifters after the PL is powered up and before the signals are used. The PS must be powered on to
program the logic in the PL.
Example: Power-up Sequence
1. Power-up the PL. Refer to the data sheet for voltage sequencing requirements. The
slcr.LVL_SHFTR_EN register should be equal to 0x0.
2. Enable the PS-to-PL level shifters. Write 0x0A to the slcr.LVL_SHFTR_EN register.
3. Program the PL.
4. Wait for the PL to be programmed. Read devcfg.INT_STS [PCFG_DONE_INT] until = 1 to
indicate that the DONE signals has asserted.
5. Enable the PL-to-PS level shifters. Write 0x0F to the slcr.LVL_SHFTR_EN register.
6. Begin to use the signals and interfaces between the PS and PL.
Example: Power-down Sequence
1. Stop using the signals and interfaces between the PS and PL.
2. Disable the voltage level shifters. Write 0x0 to the slcr.LVL_SHFTR_EN register.
3. Power-down the PL. Refer to the data sheet for voltage sequencing requirements.
4. Leave the slcr.LVL_SHFTR_EN register = 0x0 when the PL is powered down.
TIP: Functionally, there is no reason to enable the voltage level shifters until the PL is fully configured.
The PS does not allow the voltage level shifters to be enabled until the PL global signals indicate that
it is safe to do so. The PL is fully programmed when the PL DONE signal is High. The PL DONE signal
is tracked as an interrupt in the DevC subsystem.