User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 462
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
qTD DWord 3 to 7: Buffer page Pointer List
The last five DWords of a queue element transfer descriptor is an array of physical memory address
pointers. These pointers reference the individual pages of a data buffer.
The HCD initializes current offset field to the starting offset into the current page, where current
page is selected via the value in the C_Page field.
The field C_Page specifies the current active pointer. When the transfer element descriptor is
fetched, the starting buffer address is selected using C_Page (similar to an array index to select an
array element). If a transaction spans a 4 KB buffer boundary, the host controller must detect the
page-span boundary in the data stream, increment C_Page and advance to the next buffer pointer in
the list, and conclude the transaction via the new buffer pointer.
3 Transaction Error Status. Set to a 1 by the host controller during status update in the case where
the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). If the
controller sets this bit to a 1, then it remains a 1 for the duration of the transfer.
2 Missed Microframe Status. This bit is ignored unless the QH.EPS field indicates a full- or low-speed
endpoint and the queue head is in the periodic list. This bit is set when the host controller detected
that a host-induced hold-off caused the controller to miss a required complete-split transaction. If
the controller sets this bit to a 1, then it remains a 1 for the duration of the transfer.
1 Split Transaction State Status. This bit is ignored by the host controller unless the QH.EPS field
indicates a FS or LS endpoint. When a Full- or Low speed device, the host controller uses this bit to
track the state of the split transaction. The functional requirements of the controller for managing
this state bit and the split transaction protocol depends on whether the endpoint is in the periodic
or asynchronous schedule.
• 0: Do Start Split. This value directs the host controller to issue a Start split transaction to the
endpoint.
• 1: Do Complete Split. This value directs the host controller to issue a Complete split transaction
to the endpoint.
0 Ping State/ERR Status. If the QH.EPS field indicates a HS device and the PID indicates an OUT
endpoint, then this is the state bit for the Ping protocol.
• 0: Do OUT. This value directs the controller to issue an OUT PID to the endpoint.
• 1: Do Ping. This value directs the controller to issue a Ping PID to the endpoint.
If the QH.EPS field does not indicate a HS device, then this field is used as an error indicator bit. It
is set to a 1 by the controller whenever a periodic split-transaction receives an ERR handshake.
Table 15-39: USB Host qTD DWord 3 to 7: Buffer Pointers
Bits Description
31:1
2
DWords 3 to 7: Buffer Pointer. 4KB page-aligned memory address.
11:0 DWord 3: Current Offset. Byte offset into the active page (as selected by C_Page). The host controller
is not required to write this field back when the qTD is retired.
DWords 4 to 7: Reserved. Field reserved and should be set to 0.
Table 15-38: USB Host qTD DWord 2: DT, Total Bytes (Cont’d)
Bits Description