User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 463
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.12.6 Queue Head (QH)
The first three DWords of the QH include Static State information about the endpoint. The current
qTD pointer is the system memory address pointer for the current qTD and is updated by the
hardware when a new qTD is written (overlaid) in the QH’s overlay area.
QH Horizontal Link Pointer, DWord 0
The first DWord of a Queue Head contains a link pointer to the next data object to be processed after
any required processing in this queue has been completed, as well as the control bits defined below.
This pointer can reference a queue head or one of the isochronous transfer descriptors. It must not
reference a queue element transfer descriptor.
Table 15-40: USB Host Queue Head (QH) Descriptor Format
Reference Type 3130292827262524232221201918171615 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 DWord
Table 15-41
Static
Endpoint
State
Queue Head Horizontal Link Pointer 00 TYP T
0
Table 15-42
RL C Maximum Packet Length H DTC EPS EndPt I Device Address
1
Mult Port Number * Hub Addr * uFrame C-mask * uFrame S-mask 2
Table 15-43
Current Pointer
Current qTD Pointer 00000 3
Table 15-44
Transfer Overlay Area
Next qTD Pointer 0000 T 4
Transfer Results
Area
Alternate Next qTD Pointer NakCnt T 5
DT Total Bytes
IOC
C_Page Cerr PID Status P 6
Buffer Pointer (Page 0) Current Offset 7
Buffer Pointer (Page 1) reserved C-prog-mask * 8
Buffer Pointer (Page 2) S-Bytes * Split_Frame_Tag * 9
Table 15-45
Buffer Pointer (Page 3) reserved 10
Buffer Pointer (Page 4) reserved 11
Host Controller Read/Write Host Controller Read-only
* means these fields are used exclusively to support Split Transactions to USB 2.0 Hubs.
Table 15-41: USB Host QH DWord 0: Link Pointer
Bits Description
31:5 Queue Head Horizontal Link Pointer. System memory address of the next data object in the
periodic list.
4:3 Reserved. Field reserved and should be set to 0.
2:1
Transaction Descriptor Type, TYP. Set to 01 (QH type). Refer to section 15.12.2 Transfer Descriptor
Type (TYP) Field for general information.
0 Termination Bit, T.
Periodic List Schedule response:
0: link to the next QH; the Queue Head Horizontal Link Pointer field is valid.
1: end of the periodic list processing; the pointer field is invalid.
Asynchronous Schedule response: Ignored.