User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 464
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
QH DWords 1 and 2: Endpoint Capabilities and Characteristics
The second and third DWords of a Queue Head specifies static information about the endpoint. This
information does not change over the lifetime of the endpoint. The host controller must not modify
the bits in these DWords.
Table 15-42: USB Host QH DWords 1 and 2: Endpoint Capabilities and Characteristics
Bits Description
DWord 1: Capabilities and Characteristics.
These are the USB endpoint characteristics including addressing, maximum packet size, and endpoint speed.
31:28 NAK Count Reload, RL. This field contains a value, which is used by the host controller to reload the
NAK Counter field.
27 Control Endpoint Flag, C. If the QH.EPS field indicates the endpoint is not a high speed device, and
the endpoint is a control endpoint, then the HCD must set this bit to a 1. Otherwise, it should always
set this bit to a 0.
26:16 Maximum Packet Length. This directly corresponds to the maximum packet size of the associated
endpoint (wMaxPacketSize). The maximum value this field can contain is 400h (1,024).
15 Head of Reclamation List Flag, H. This bit is set by the HCD to mark a queue head as being the head
of the reclamation list.
14 Data Toggle Control, DTC. This bit specifies where the host controller should get the initial data
toggle on an overlay transition.
• 0: Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head.
• 1: Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the
queue head from the DT bit in the qTD.
13:12 Endpoint Speed, EPS. Select speed of the associated endpoint.
• 00: Full-Speed (12Mb/s)
• 01: Low-Speed (1.5Mb/s)
• 10: High-Speed (480Mb/s)
• 11: Reserved
11:8 Endpoint Number, EndPt. This 4-bit field selects the particular endpoint number on the device
serving as the data source or sink.
7 Inactivate on Next Transaction, I. The HCD requests that the host controller set the Active status bit
to 0. This field is only valid when the QH is in the Periodic Schedule and the QH.EPS field indicates
an FS or LS endpoint. Setting this bit to a 1 when the queue head is in the Asynchronous Schedule
or the QH.EPS field indicates a high-speed device yields undefined results.
6:0 Device Address. Select the specific device serving as the data source or sink.
DWord 2: Capabilities and Characteristics
These are adjustable parameters of the endpoint. They affect how the endpoint data stream is managed by
the host controller.
31:30 High-Bandwidth Pipe Multiplier, Mult. This field is a multiplier used to key the host controller as the
number of successive packets the host controller can submit to the endpoint in the current execution.
The host controller makes the simplifying assumption that the HCD properly initializes this field
(regardless of location of queue head in the schedules or other run time parameters).
• 00: Reserved. A 0 in this field yields undefined results.
• 01: One transaction to be issued for this endpoint per microframe.
• 10: Two transactions to be issued for this endpoint per microframe.
• 11: Three transactions to be issued for this endpoint per microframe.