User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 465
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
uFrame C-Mask
The split completion mask field, QH.uFRAME C-Mask, is ignored by the host controller unless the
QH.EPS field indicates this device is LS or FS and this QH is in the periodic list. This field (along with
the Active and SplitX-state fields) is used to determine which microframes the host controller should
execute a complete-split transaction. This field is a straight bit position field, so if bit [0] is set then
the complete-split transaction should occur in the first microframe, if bit 1 is set then it should occur
in the second microframe, and so on.
When the criteria for using this field are met, a 0 value in this field has undefined behavior. This field
is used by the host controller to match against the three low-order bits of the FRINDEX register. If the
FRINDEX register bits decode to a position where the QH.uFrame C-Mask field is a 1, then this queue
head is a candidate for transaction execution. There can be more than one bit in this mask set.
The C-Mask can be set for multiple micro frames, as it is not known in which microframe the
transaction will complete. So the C-Mask can be set for the micro frame after the S-Mask and all
subsequent micro fames thereafter. The C-Mask field should not have a bit set to the same
microframe as the S-Mask is set to.
uFrame S-mask
The interrupt schedule mask field, QH.uFrame S-mask, is used for all endpoint speeds. The HCD
should set this field = 0 when the QH is on the asynchronous schedule. A non-zero value in this field
indicates an interrupt endpoint.
The host controller uses the value of the three low-order bits of the FRINDEX register as an index into
a bit position in this bit vector. If the QH.uFrame S-mask field has a 1 at the indexed bit position then
this queue head is a candidate for transaction execution.
If the QH.EPS field indicates the endpoint is a high-speed endpoint, then the transaction executed is
determined by the PID field contained in the execution area.
This field is also used to support split transaction types: Interrupt (IN/OUT). This condition is true
when this field is non-zero and the QH.EPS field indicates this is either a full- or low-speed device.
29:23 Port Number. This is used in the split-transaction protocol.This field is ignored by the host controller
unless the QH.EPS field indicates a full- or low-speed device. The value is the port number identifier
on the USB 2.0 Hub (for hub at device address Hub Addr below), below which the full- or low-speed
device associated with this endpoint is attached.
22:16 Hub Address, Hub Addr. This field is used in the split-transaction protocol. This field is ignored by
the host controller unless the QH.EPS field indicates a full-or low-speed device. The value is the USB
device address of the USB 2.0 Hub below which the full- or low-speed device associated with this
endpoint is attached.
15:8 Split Completion Mask, uFrame C-Mask. Refer to the text.
7:0 Interrupt Schedule Mask, uFrame S-mask. Refer to the text.
Table 15-42: USB Host QH DWords 1 and 2: Endpoint Capabilities and Characteristics (Cont’d)
Bits Description