User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 467
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Alternate Next qTD Pointer
15
31:5 Alternate Next qTD Pointer.
4:1 NAK Counter, NakCnt. This field is a counter the host controller decrements whenever a
transaction for the endpoint associated with this queue head results in a Nak or Nyet
response.
This counter is reloaded from RL before a transaction is executed during the first pass of the
reclamation list (relative to an Asynchronous List Restart condition). It is also loaded from RL
during an overlay.
0 Terminate transfer, T.
• 0: link to the Alternate Next qTD Pointer field; the address is valid.
• 1: end the transaction, the Alternate Next qTD Pointer field is not valid.
Total Bytes
26
31 Data toggle, DT. The Data Toggle Control controls whether the host controller preserves this
bit when an overlay operation is performed.
30:16 Total Bytes. Refer to
section Total Bytes to Transfer Parameter for more info.
15 Interrupt On Complete, IOC. The IOC control bit is always inherited from the source qTD
when the overlay operation is performed.
14:12 C_Page.
11:10 Error Counter, Cerr. This two-bit field is copied from the qTD during the overlay and written
back during queue advancement.
9:8 Port ID, PID.
7:0 Reserved. Write 0.
0 Ping State, /PERR. If the QH.EPS field indicates a high-speed endpoint, then this field should
be preserved during the overlay operation.
Buffer Pointer (page 0)
37
31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12].
11:0 Current Offset.
Buffer Pointer (page 1)
48
31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12].
11:8 Reserved.
7:0 QH (split transactions only): C-prog-mask.
qTD and non-split QH: Reserved.
Buffer Pointer (page 2)
59
31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12].
11:5 S-bytes. This field is used to keep track of the number of bytes sent or received during an IN
or OUT split transaction. The HCD must ensure that the S-bytes field in a qTD is 0 before
activating the qTD.
4:0 Split-transaction Frame Tag, Split_Frame_Tag. This field is used to track the progress of an
interrupt split-transaction. This field is initialized to 0 during any overlay.
Table 15-44: USB Host Transfer Overlay Descriptors (Cont’d)
Bits Description
qTD
DWord
QH
DWord