User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 470
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.14.1 Hardware Assistance Features
The hardware assist mechanisms provide automated response and sequencing that might not be
possible using software due to significant interrupt latency response times. The use of this additional
circuitry is optional and can be used to assist the three sequences below.
• Auto-Reset [HAAR]: Reset after a connect event.
• Data-Pulse [HADP]: Generates a 7 ms pulse on the DP signal.
• B-Disconnect to A-Connect Event [HABA].
Auto-Reset Option
When the usb.OTGSC [HAAR] bit is set to 1, the host controller will automatically start a reset after a
connect event. This shortcuts the normal process where the software is notified of the connect event
and starts the reset. The software will still receive notification of the connect event but should not
write the reset bit when the [HAAR] bit is set = 1. The software will be notified again after the reset
is complete via the enable change bit in the PORTSC1 register which cause a port change interrupt.
This hardware assistance feature will ensure the OTG parameter TB_ACON_BSE0_MAX = 1 ms is met.
Data-Pulse
Writing a 1 to usb.OTGSC [HADP] bit will start a data pulse of approximately 7 ms in duration and
then automatically cease the data pulsing. During the data pulse, the DP signal will be set and then
cleared. This automation relieves the software from accurately controlling the data-pulse duration.
During the data pulse, the HCD can poll to see that the [HADP] and [DP] bits have returned low to
recognize the completion or simply launch the data pulse and wait to see if a VBUS Valid interrupt
occurs when the A-side supplies bus power.
This hardware assistance feature will ensure data pulsing meets the OTG requirement of > 5 ms and
< 10 ms.
B-Disconnect to A-Connect
During HNP, the B-Disconnect occurs from the OTG A_suspend state and within 3 ms, the A-device
must enable the pull-up on the DP signal in the A-peripheral state. When usb.OTGSC [HABA] is set =
1, the Host Controller port is in suspend mode, and the device disconnects, then this hardware assist
begins.
1. Reset the OTG controller.
2. Set the OTG controller into device mode.
3. Write the device run bit to a 1 and enable necessary interrupts including:
4. USB Reset Enable [URE]; enables interrupt on USB bus reset to device
5. Sleep Enable [SLE]; enables interrupt on device suspend
6. Port Change Detect Enable [PCE]; enables interrupt on device connect