User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 471
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
When the HCD has enabled this hardware assist, it must not interfere during the transition and
should not write any control registers until it gets an interrupt from the device controller signifying
that a reset interrupt has occurred or at least first verify that the controller has entered device mode.
The HCD must not activate the soft reset at any time since this action is performed by hardware.
During the transition, the HCD might see an interrupt from the disconnect and/or other spurious
interrupts (i.e., SOF/etc.) that might or might not cascade and can be cleared by the soft reset
depending on the HCD response time.
After the controller has entered device mode by the hardware assist, the HCD must ensure that the
usb.ENDPTLISTADDR is programmed properly before the host sends a setup packet. Since the end of
the reset duration, which can be initiated quickly (a few microseconds) after connect, will require at
a minimum 50 ms, this is the time for which the HCD must be ready to accept setup packets after
having received notification that the reset has been detected or simply that the OTG is in device
mode whichever occurs first.
In the case where the A-peripheral fails to see a reset after the controller enters device mode and
engages the DP-pull-up, the interrupt software signifying that a suspend has occurred.
This assist will ensure the parameter TA_BDIS_ACON_MAX = 3 ms is met.
15.14.2 OTG Interrupt and Control Bits
The interrupt and control bits are included in one register, the OTGSC register. Changes in the status
activity will latched events. The status bits indicate the current activity. Software reads the latched
events and status activity bits to determine there was an event and its status. The IRQ interrupt signal
to the GIC interrupt controller will be asserted to the GIC interrupt controller when both the interrupt
enable bit (controlled by software) and the associated status activity bit (controlled by hardware) are
equal to 1.
Table 15-48: USB OTG Status/Interrupt and Control Bits in the OTGSC Register
Interrupts Control Bits
3130292827262524232221201918171615141312111098765432 1 0
r Enable (R/W) r Latched Event (W1C) r Status (read-only) HABA HADP IDPU DP OT HAAR VC VD
Interrupts:
• Status Activity
• Latched Events
•Interrupt Enable
Data Pulse
1 ms
B Session End
B Session Valid
A Session Valid
A VBus
USB ID
0: VD: Vbus Discharge enable (rw)
1: VC: VBus Charge enable (rw)
2: HAAR: Hardware Auto-Reset enable (rw)
3: OT: OTG Device mode DP M pull-down enable (rw)
4: DP: Assert DP pull-up during SRP (rw)
5: IDPU: ID Pull-up enable (rw)
6: HADP: Hardware Assist Data-pulse generator (rw)
7: HABA: Hardware Assist B-disconnect to A-connect (rw)