User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 474
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
fs
15.15.3 System Interrupt
Each controller sends its own IRQ interrupt to the GIC interrupt controller and to the EMIO interface
based on events within the controller. Controller 0 generates IRQ #53 and controller 1 generates IRQ
#76. These are shown in more detail in section 7.2.3 Shared Peripheral Interrupts (SPI).
The individual host and device mode interrupts can be read and cleared using the usb.USBSTS
register and masked using the usb.USBINTR register. These interrupts are described in section
15.3.5 Interrupt and Status Bits Overview.
The individual OTG interrupts are contained in the usb.OTGSC register and described in section
15.14.2 OTG Interrupt and Control Bits.
15.15.4 APB Slave Interface
The 32-bit APB slave interface is used by the software to read and write the control and status
registers. The interface is AMBA 3.0 compatible. All signals are used except PRESET_N and PSLVERR.
15.15.5 AHB Master Interface
The 32-bit AHB master interface is used by the DMA controller to read and write data packets and
transfer descriptors. The interface is AMBA 3.0 compatible.
Unused Signals
All of the AHB interface signals are used except:
• PROT[3:0] are tied to 0001 (non-cacheable transactions).
Table 15-49: USB Resets Summary List
Reset Name
Controller
State
Registers IRQ Reference
PS System Reset
AMBA (APB/AHB) Interface Reset
slcr.USB_RST_CTRL [USBx_CPU1X_RST]
Yes Yes no
Chapter 26, Reset System.
Reset values: Appendix B,
Register Details.
usb.USBCMD [RST]
(partial controller reset)
Partial no Device and Host Modes
OTG mode Auto-Reset
Hardware Assistance usb.USBOTG [HAAR]
no
Section 15.14.1 Hardware
Assistance Features
PHY reset
Output from PS GPIO controller
no effect no effect
no
Chapter 15, USB Host, Device,
and OTG Controller
Send USB Reset (Host Mode) no effect no effect no Software Example.
Receive USB Reset (Device Mode) no effect no effect [URI] Software Example.