User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 48
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
2.5.2 IOP Interface Connections
For most peripherals, there is flexibility in where the I/O signals can be mapped. The routing
capabilities are shown in Figure 2-4. For example, the XPS design software includes up to 12 possible
MIO port mappings for CAN, or, if selected, a path to the EMIO interface. The peripheral system
connection diagram is shown in Figure 2-3.
The majority of the I/O signals for PS peripherals, other than USB, can be routed to either the PS pins
through the MIO, or to the PL pins through the EMIO. Most peripherals also maintain the same
protocol between MIO and EMIO, except Gigabit Ethernet. To reduce pin count, a 4-bit RGMII
interface runs through the MIO at a 250 MHz data rate (125 MHz clock with a double data rate). The
route through the EMIO includes an 8-bit GMII interface running at a 125 MHz data rate. The USB,
Quad-SPI, and SMC interfaces are not available to the EMIO interface to the PL.
Table 2-3: I/O Peripheral MIO-EMIO Interface Routing
Peripheral MIO Routing EMIO Routing Cross Reference
TTC [0,1]
Clock In, Wave Out.
One pair of signals from
each counter.
Clock In, Wave Out.
Three pairs of signals
from each counter.
See Chapter 8, Timers
SWDT Clock In, Reset Out Clock In, Reset Out See Chapter 8, Timers
SMC
Parallel NOR/SRAM and
NAND Flash
Not available
See Chapter 11, Static Memory
Controller
Quad-SPI [0,1]
Serial, dual and quad
modes
Not available
See Chapter 12, Quad-SPI Flash
Controller
SDIO [0,1] 50 MHz 25 MHz See Chapter 13, SD/SDIO Controller
GPIOs
Up to 54 I/O channels
(GPIO Banks 0 and 1)
64 GPIO channels with
input, output, 3-state
control (GPIO banks 2
and 3)
See Chapter 14, General Purpose I/O
(GPIO)
USB [0,1] Host, device, and OTG Not available
See Chapter 15, USB Host, Device, and
OTG Controller
Ethernet [0,1] RGMII v2.0 MII/GMII
(1)
See Chapter 16, Gigabit Ethernet
Controller
SPI [0,1] 50 MHz Available See Chapter 17, SPI Controller
CAN [0,1]
ISO 11898 -1,
CAN 2.0A/B
Available See Chapter 18, CAN Controller
UART [0,1]
Simple UART:
Two pins (TX/RX)
TX, RX, DTR, DCD, DSR,
RI, RTS and CTS
See Chapter 19, UART Controller
I2C [0,1] SCL, SDA {0, 1} SCL, SDA {0, 1} See Chapter 20, I2C Controller
PJTAG TCK, TMS, TDI, TDO
TCK, TMS, TDI, TDO,
3-state for TDO
See Chapter 27, JTAG and DAP
Subsystem
Trace Port IU Up to 16-bit data Up to 32-bit data See Chapter 28, System Test and Debug
Notes:
1. When the Ethernet MII/GMII interface is routed through EMIO, other MII interfaces (e.g., RMII, RGMII, and SGMII)
can be derived using appropriate shim logic in the PL that attaches to PL pins.