User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 482
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
16.2 Functional Description and Programming
Model
The controller comprises four main components:
• MAC controlling transmit, receive, address checking, and loopback
• Control and status registers, statistics registers, and synchronization logic
• DMA controlling data transmit and receive through an AHB master interface
• Time stamp unit (TSU) for calculating the IEEE 1588 timer values
10/100/1000 Operation
The gigabit enable bit in the Network Configuration register selects between 10/100 Mb/s Ethernet
operation and 1000 Mb/s mode. The 10/100 Mb/s speed bit in the network configuration register is
used to select between 10 Mb/s and 100 Mb/s.
MDIO Interface
Both controllers provide MDIO interfaces, however, only one interface is needed to control both of
the external PHYs due to the difference in PHY address.
16.2.1 MAC Transmitter
The MAC transmitter can operate in either half duplex or full duplex mode, and transmits frames in
accordance with the Ethernet IEEE 802.3 standard. In half duplex mode, the CSMA/CD protocol of the
IEEE 802.3 specification is followed.
Frame assembly starts by adding the preamble and the start frame delimiter. Data is taken from the
transmit FIFO a word at a time. When the controller is configured for gigabit operation, the data
output to the PHY uses all eight bits of the txd[7:0] output. In 10/100 mode, transmit data to the PHY
is nibble wide and least significant nibble first using txd[3:0] with txd[7:4] tied to logic 0.
If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order
32 bit polynomial. This is inverted and appended to the end of the frame taking the frame length to
a minimum of 64 bytes. If the no-CRC bit is set in the second word of the last buffer descriptor of a
transmit frame, neither pad nor CRC are appended. The no-CRC bit can also be set through the FIFO.
In full duplex mode (at all data rates), frames are transmitted immediately. Back-to-back frames are
transmitted at least 96 bit times apart to guarantee the interframe gap.
In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the
signal to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the
collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits
taken from the data register and then retries transmission after the back off time has elapsed. If the
collision occurs during either the preamble or SFD, then these fields are completed prior to
generation of the jam sequence.