User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 483
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
The back off time is based on an XOR of the 10 least significant bits of the data coming from the
transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends on
the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on
up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error is indicated and no
further attempts are made if 16 consecutive attempts cause a collision. This operation is compatible
with the description in Clause 4.2.3.2.5 of the IEEE 802.3 standard which refers to the truncated binary
exponential back off algorithm.
In 10/100 mode, both collisions and late collisions are treated identically, and back off and retry are
performed up to 16 times. When operating in gigabit mode, late collisions are treated as an
exception and transmission is aborted, without retry. This condition is reported in the transmit buffer
descriptor word 1 (late collision, bit 26) and also in the Transmit Status register (late collision, bit 7).
An interrupt can also be generated (if enabled) when this exception occurs, and bit 5 in the Interrupt
Status Register is set.
When bit [28] is set in the Network Configuration register the IPG can be stretched beyond 96 bits
depending on the length of the previously transmitted frame and the value written to the
IPG_STRETCH register. The least significant 8 bits of the IPG_STRETCH register multiply the previous
frame length (including preamble) the next significant 8 bits (+1 so as not to get a divide by zero)
divide the frame length to generate the IPG. IPG stretch only works in full duplex mode and when bit
28 is set in the Network Configuration register. The IPG_STRETCH register cannot be used to shrink
the IPG below 96 bits.
If the back pressure bit is set in the Network Control register or if the half_duplex_flow_control_en
input is set in 10M or 100M half duplex mode, the transmit block transmits 64 bits of data, which can
consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force
a collision. This provides a way of implementing flow control in half duplex mode.
16.2.2 MAC Receiver
All processing within the MAC receiver uses 16-bit data paths. The MAC receiver checks for valid
preamble, FCS, alignment, and length. It then sends the received frames to the FIFO (to either the
DMA controller or external to the IP core) and stores the frames destination address for use by the
address checking block.
If, during frame reception, the frame is found to be too long, a bad frame indication is sent to the
FIFO. The receiver logic ceases to send data to memory as soon as this condition occurs.
At end of frame reception the receive block indicates to the DMA block whether the frame is good
or bad. The DMA block recovers the current receive buffer if the frame was bad.
Ethernet frames are normally stored in DMA memory or to the FIFO complete with the FCS. Setting
the FCS remove bit in the network configuration register (bit [17]) causes frames to be stored
without their corresponding FCS. The reported frame length field is reduced by four bytes to reflect
this operation.
The receive block signals to the register block to increment the alignment, CRC (FCS), short frame,
long frame, jabber or receive symbol errors when any of these exception conditions occur.
If bit [26] is set in the network configuration CRC errors are ignored and frames with CRC errors are
not discarded, though the Frame Check Sequence Errors Statistic register is still incremented. Bit[13]