User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 484
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
of the receiver descriptor word 1 is updated to indicate the FCS validity for the particular frame. This
is useful for applications where individual frames with FCS errors must be identified.
Received frames can be checked for length field error by setting the length field error frame discard
bit of the Network Configuration register (bit [16]). When this bit is set, the receiver compares a
frame's measured length with the length field (bytes 13 and 14) extracted from the frame. The frame
is discarded if the measured length is shorter. This checking procedure is for received frames
between 64 bytes and 1,518 bytes in length.
Each discarded frame is counted in the 10-bit length field Error Statistics register. Frames where the
length field is greater than or equal to 0x0600 are not checked.
16.2.3 MAC Filtering
The MAC filter determines which frames should be written to the AHB interface FIFO and onto the
DMA controller.
Whether a frame is passed depends on what is enabled in the Network Configuration register, the
state of the external matching pins, the contents of the specific address, type, and hash registers and
the frame's destination address and type field.
If bit [25] of the Network Configuration register is not set, a frame is not copied to memory if the
Gigabit Ethernet controller is transmitting in half duplex mode at the time a destination address is
received.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits)
of an Ethernet frame make up the destination address. The first bit of the destination address, which
is the LSB of the first byte of the frame, is the group or individual bit. This is one for multicast
addresses and zero for unicast. The all-ones address is the broadcast address and a special case of
multicast.
The Gigabit Ethernet controller supports recognition of four specific addresses. Each specific address
requires two registers, Specific Address register bottom and Specific Address register top. Specific
address register bottom stores the first four bytes of the destination address and Specific Address
register top contains the last two bytes. The addresses stored can be specific, group, local or
universal.
The destination address of received frames is compared against the data stored in the Specific
Address registers once they have been activated. The addresses are deactivated at reset or when
their corresponding Specific Address register bottom is written. They are activated when Specific
Address register top is written. If a receive frame address matches an active address, the frame is
written to the FIFO and on to DMA controller, if used.
Frames can be filtered using the type ID field for matching. Four type ID registers exist in the register
address space and each can be enabled for matching by writing a one to the MSB (bit [31]) of the
respective register. When a frame is received, the matching is implemented as an OR function of the
various types of match.
The contents of each type ID registers (when enabled) are compared against the length/type ID of
the frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames)
and copied to memory if a match is found. The encoded type ID match bits (Word 0, bit [22] and bit