User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 49
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
On the interconnect side, the USB, Ethernet and SDIO peripherals are connected to the central
interconnect to service the six DMA masters. Software accesses the slave-only Quad-SPI and SMC
peripherals via the AHB interconnect. The GPIO, SPI, CAN, UART, and I2C save-only controllers are
accessed via the APB bus. All control and status registers are also accessed via the APB interconnect
except for the SDIO controllers which each have two AHB interfaces. This architecture is designed to
balance the bandwidth needs of each controller interface.
X-Ref Target - Figure 2-3
Figure 2-3: I/O Peripherals System Diagram
UG585_c2_03_121613
RGMII 0
Comm
Port
GigE 0
ULPI 1
ULPI 0
to EMIO
MDIO 0
AHB 32
APB
AXI 32
MIO
[0]
MIO
[1]
MIO
[2]
MIO
[51]
MIO
[52]
MIO
[53]
MIO
[6]
MIO
[7]
MIO
[8]
MIO
[9]
MIO
[10]
DMA
Regs
RGMII 1
Comm
Port
GigE 1
AHB 32
APB
DMA
Regs
USB 0
WAVE_OUT
CLK_IN
TTC 1, 0
GMII via EMIO
to EMIO
RESET_OUT
CLK_IN
SWDT
Central
Interconnect
Slave
Interconnect
Zynq
Device
Pins
PS
AHB 32
APB
DMA
Regs
USB 1
AHB 32
APB
DMA
Regs
QSPI 1
SMC
ONFi
Parallel
GPIO
QSPI 0
Quad SPI 0
Quad SPI 1
NAND
NOR/SRAM
AXI 32
APB
DMA
Regs
Data Path
Regs
AXI 32
APB
APB
APB
APB
APB
APB
APB
DMA
Regs
SDIO 1
SDIO 0
SDIO 0
Boot Mode
Pins:
MIO[5:2]
Flash/JPEG
MIO[6]
PLL Bypass
MIO[8:7]
Voltage Mode
AHB 32
DMA
Regs
SDIO 1
AHB 32
AHB 32
AHB 32
DMA
Regs
AXI 32
M
AXI 32
S
AXI 32
GPIO Banks 0 & 1
GPIO Banks 2 & 3
SPI {0, 1}
CAN {0, 1}
EMIO
Programmable Logic (PL)
UART {0, 1}
I2C {0, 1}
Control,
Status Regs
To APB slave ports for Regs
Boot DevicesPLLVMODE
Dervice
Boundary
IOPs MIO
Slave
S
S
S
S
S
S
M
S
M
M
M
M
S
M
M
M
M
M
M
to EMIO
Port/PWR
Port/PWR