User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 490
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Word 1
31 Global all ones broadcast address detected.
30 Multicast hash match.
29 Unicast hash match.
28 Reserved.
27 Specific address register match found,. bit 25 and bit 26 indicate which specific address register
causes the match.
26:25 Specific address register match. Encoded as follows:
00b: Specific address register 1 match
01b: Specific address register 2 match
10b: Specific address register 3 match
11b: Specific address register 4 match
If more than one specific address is matched only one is indicated with priority 4 down to 1.
24 This bit has a different meaning depending on whether RX checksum offloading is enabled.
• With RX checksum offloading disabled: (bit [24] clear in Network Configuration) Type ID register
match found, bit [22] and bit [23] indicate which type ID register causes the match.
• With RX checksum offloading enabled: (bit [24] set in Network Configuration)
0b: The frame was not SNAP encoded and/or had a VLAN tag with the CFI bit set.
1b: The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit not
set.
23:22 This bit has a different meaning depending on whether RX checksum offloading is enabled.
With RX checksum offloading disabled: (bit [24] clear in Network Configuration) Type ID register
match. Encoded as follows:
00b: Type ID register 1 match
01b: Type ID register 2 match
10b: Type ID register 3 match
11b: Type ID register 4 match
If more than one Type ID is matched only one is indicated with priority 4 down to 1.
With RX checksum offloading enabled: (bit [24] set in Network Configuration)
00b: Neither the IP header checksum nor the TCP/UDP checksum was checked.
01b: The IP header checksum was checked and was correct. Neither the TCP or UDP checksum
was checked.
10b: Both the IP header and TCP checksum were checked and were correct.
11b: Both the IP header and UDP checksum were checked and were correct.
21 VLAN tag detected – type ID of
0x8100. For packets incorporating the stacked VLAN processing
feature, this bit is set if the second VLAN tag has a type ID of
0x8100.
20 Priority tag detected – type ID of
0x8100 and null VLAN identifier. For packets incorporating the
stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100
and a null VLAN identifier.
19:17 VLAN priority – only valid if bit [21] is set.
16 Canonical format indicator (CFI) bit – only valid if bit 21 is set.
15 End of frame – when set the buffer contains the end of a frame. If end of frame is not set, then the
only valid status bit is start of frame (bit 14).
Table 16-2: Rx Buffer Descriptor Entry (Cont’d)
Bit Function