User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 491
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
The start location of the receive-buffer descriptor list must be written with the receive-buffer queue
base address before reception is enabled (receive enable in the Network Control register). Once
reception is enabled, any writes to the Receive-buffer Queue Base Address register are ignored.
When read, it returns the current pointer position in the descriptor list, though this is only valid and
stable when receive is disabled.
If the filter block indicates that a frame should be copied to memory, the receive data DMA
operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered.
An internal counter represents the receive-buffer queue pointer and it is not visible through the CPU
interface. The receive-buffer queue pointer increments by two words after each buffer has been
used. It re-initializes to the receive-buffer queue base address if any descriptor has its wrap bit set.
As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the
descriptor to logic one indicating the AHB buffer has been used.
Software should search through the “used” bits in the AHB buffer descriptors to find out how many
frames have been received, checking the start of frame and end of frame bits.
Received frames are written out to the AHB buffers as soon as enough frame data exists in the packet
buffer. This might mean that several full AHB buffers are used before some error conditions can be
detected. If a receive error is detected the receive buffer currently being written is recovered.
Previous buffers are not recovered. For example, when receiving frames with CRC errors or excessive
length, it is possible that a frame fragment might be stored in a sequence of AHB receive buffers.
Software can detect this by looking for the start of frame bit set in a buffer following a buffer with no
end of frame bit set.
For a properly working 10/100/1000 Ethernet system there should be no excessive length frames or
frames greater than 128 bytes with CRC errors. Collision fragments are less than 128 bytes long,
therefore it is a rare occurrence to find a frame fragment in a receive AHB buffer, when using the
default value of 128 bytes for the receive buffers size.
14 Start of frame – when set the buffer contains the start of a frame. If both bits 15 and 14 are set, the
buffer contains a whole frame.
13 This bit has a different meaning depending on whether ignore FCS mode are enabled. This bit is
zero if ignore FCS mode is disabled.
With ignore FCS mode enabled: (bit [26] set in Network Configuration Register). This indicates per
frame FCS status as follows:
0b: Frame had good FCS.
1b: Frame had bad FCS, but was copied to memory as ignore FCS enabled.
12:0 These bits represent the length of the received frame which might or might not include FCS
depending on whether FCS discard mode is enabled.
• With FCS discard mode disabled: (bit [17] clear in Network Configuration Register) Least
significant 12-bits for length of frame including FCS.
• With FCS discard mode enabled: (bit [17] set in Network Configuration Register) Least significant
12-bits for length of frame excluding FCS.
Table 16-2: Rx Buffer Descriptor Entry (Cont’d)
Bit Function