User manual

Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 492
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Only good received frames are written out of the DMA, so no fragments exist in the AHB buffers due
to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used
bit read on the second buffer of a multi-buffer frame.
If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the
location of the receive AHB buffer, then the buffer has been already used and cannot be used again
until software has processed the frame and cleared bit zero. In this case, the “buffer not available” bit
in the Receive Status register is set and an interrupt is triggered. The receive resource error statistics
register is also incremented.
The user can optionally select whether received frames should be automatically discarded when no
AHB buffer resource is available. This feature is selected via bit [24] of the DMA Configuration
register (by default, the received frames are not automatically discarded). If this feature is off, then
received packets remain stored in the packet buffer until an AHB buffer resource next becomes
available. This can lead to an eventual packet buffer overflow if packets continue to be received when
bit zero (used bit) of the receive-buffer descriptor remains set. Note that after a used bit has been
read, the receive-buffer manager re-reads the location of the receive buffer descriptor every time a
new packet is received.
A receive overrun condition occurs when the receive packet buffer is full, or because hresp was not
okay. In all other modes, a receive overrun condition occurs when either the AHB bus was not
granted quickly enough, or because hresp was not okay, or because a new frame has been detected
by the receive block, but the status update or write back for the previous frame has not yet finished.
For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently
being written is recovered. The next frame that is received whose address is recognized reuses the
buffer.
A write to bit [18] of the Network Control register forces a packet from the receive packet buffer to
be flushed. This feature is only acted upon when the RX DMA is not currently writing packet data out
to AHB – i.e., it is in an IDLE state. If the RX DMA is active, a write to this bit is ignored.
Tx Buffers
Frames to transmit are stored in one or more transmit AHB buffers. It should be noted that zero
length AHB buffers are allowed and that the maximum number of buffers permitted for each
transmit frame is 128.
The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer
descriptors at a location pointed to by the transmit-buffer queue pointer. The base address for this
queue pointer is set in software using the Transmit-buffer Queue Base Address register. Each list
entry consists of two words. The first is the byte address of the transmit buffer and the second
containing the transmit control and status. For the packet buffer DMA, the start location for each
AHB buffer is a byte address, the bottom bits of the address being used to offset the start of the data
from the data-word boundary For the FIFO based DMA, the address of the buffer is also a byte
address. Frames can be transmitted with or without automatic CRC generation. If CRC is
automatically generated, pad will also be automatically generated to take frames to a minimum
length of 64 bytes. When CRC is not automatically generated (as defined in word 1 of the transmit
buffer descriptor or through the control bus of the FIFO), the frame is assumed to be at least 64 bytes
long and pad is not generated.