User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 493
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address
to bits [31:0] in the first word of each descriptor list entry.
The second word of the transmit-buffer descriptor is initialized with control information that
indicates the length of the frame, whether or not the MAC is to append CRC, and whether the buffer
is the last buffer in the frame.
After transmission the status bits are written back to the second word of the first buffer along with
the used bit. Bit [31] is the used bit which must be zero when the control word is read if transmission
is to take place. It is written to one when the frame has been transmitted. Bits[29:20] indicate various
transmit error conditions. Bit [30] is the wrap-bit which can be set for any buffer within a frame. If no
wrap bit is encountered the queue pointer continues to increment.
The Transmit-buffer Queue Base Address register can only be updated while transmission is disabled
or halted; otherwise any attempted write is ignored. When transmission is halted the transmit-buffer
queue pointer maintains its value. Therefore, when transmission is restarted the next descriptor read
from the queue is from immediately after the last successfully transmitted frame. While transmit is
disabled (bit [3] of the network control is set Low), the transmit-buffer queue pointer resets to point
to the address indicated by the Transmit-buffer Queue Base Address register. Note that disabling
receive does not have the same effect on the receive-buffer queue pointer.
When the transmit queue is initialized, transmit is activated by writing to the transmit start bit (bit
[9]) of the Network Control register. Transmit is halted when a buffer descriptor with its used bit set
is read, a transmit error occurs, or by writing to the transmit halt bit of the Network Control register.
Transmission is suspended if a pause frame is received while the pause enable bit is set in the
network configuration register. Rewriting the start bit while transmission is active is allowed. This is
implemented with a tx_go variable which is readable in the Transmit Status register at bit location 3.
The tx_go variable is reset when:
•Transmit is disabled
• A buffer descriptor with its ownership bit set is read
• Bit [10], tx_halt, of the Network Control register is written
• There is a transmit error such as too many retries, late collision (gigabit mode only) or a transmit
under-run
To set tx_go, write to bit [9], tx_start, of the Network Control register. Transmit halt does not take
effect until any ongoing transmit finishes.
The entire contents of the frame are read into the transmit packet buffer memory, so the retry
attempt is replayed directly from the packet buffer memory rather than having to re-fetch through
the AHB.
If a used bit is read mid way through transmission of a multi buffer frame this is treated as a transmit
error. Transmission stops, tx_er is asserted and the FCS is bad.
If transmission stops due to a transmit error or a used bit being read, transmission is restarted from
the first buffer descriptor of the frame being transmitted when the transmit start bit is rewritten.
Refer to Table 16-3 for details of the transmit buffer descriptor list.