User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 494
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Table 16-3: Tx Buffer Descriptor Entry
Bit Function
Word 0
31:0 Byte address of buffer.
Word 1
31 Used – must be zero for the controller to read data to the transmit buffer. The controller sets this
to one for the first buffer of a frame once it has been successfully transmitted. Software must clear
this bit before the buffer can be used again.
30 Wrap – marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within
the frame.
29 Retry limit exceeded, transmit error detected.
28 Always set to 0.
27 Transmit frame corruption due to AHB error – set if an error occurs whilst midway through reading
transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the
buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er
asserted).
26 Late collision, transmit error detected. Late collisions only force this status bit to be set in gigabit
mode.
25:23 Reserved.
22:20 Transmit IP/TCP/UDP checksum generation offload errors:
• 000b: No Error.
• 001b: The Packet was identified as a VLAN type, but the header was not fully complete, or had
an error in it.
• 010b: The Packet was identified as a SNAP type, but the header was not fully complete, or had
an error in it.
• 011b: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of
type IPv4/IPv6.
• 100b: The Packet was not identified as VLAN, SNAP or IP.
• 101b: Non supported packet fragmentation occurred. For IPv4 packets, the IP checksum was
generated and inserted.
• 110b: Packet type detected was not TCP or UDP. TCP/UDP checksum was therefore not
generated. For IPv4 packets, the IP checksum was generated and inserted.
• 111b: A premature end of packet was detected and the TCP/UDP checksum could not be
generated.
19:17
Reserved.
16 No CRC to be appended by MAC. When set this implies that the data in the buffers already contains
a valid CRC and hence no CRC or padding is to be appended to the current frame by the MAC.
This control bit must be set for the first buffer in a frame and is ignored for the subsequent buffers
of a frame. Note that this bit must be clear when using the transmit IP/TCP/UDP checksum
generation offload, otherwise checksum generation and substitution does not occur.
15 Last buffer, when set this bit indicates that the last buffer in the current frame has been reached.
14 Reserved.
13:0 Length of buffer.