User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 497
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
In the transmit direction, the DMA continues to fetch packet data up to a limit of 256 packets, or until
the buffer is full. The size of the buffer has a maximum usable size of 4 KB.
In the receive direction, if the buffer becomes full, then an overflow occur.s An overflow also occurs
if the limit of 256 packets is breached. The size of the external buffer has a maximum usable size of
4KB.
Tx Packet Buffer
The transmitter packet buffer continues to attempt to fetch frame data from the AHB system memory
until the packet buffer itself is full, at which point it attempts to maintain its full level.
To accommodate the status and statistics associated with each frame, three words per packet are
reserved at the end of the packet data. If the packet was bad and requires to be dropped, the status
and statistics are the only information held on that packet. Storing the status in the DPRAM is
required to decouple the DMA interface of the buffer from the MAC interface, to update the MAC
status/stats, and to generate interrupts in the order in which the packets that they represent were
fetched from the AHB memory.
If any errors occur on the AHB while reading the transmit frame, the fetching of packet data from
AHB memory is halted. The MAC transmitter continues to fetch packet data, thereby emptying the
packet buffer and allowing any good non-errored frames to be transmitted successfully. When these
have been fully transmitted, the status/stats for the errored frame is updated and software is
informed via an interrupt that an AHB error occurred. This way, the error is reported in the correct
packet order.
The transmit packet buffer only attempts to read more frame data from the AHB when space is
available in the packet buffer memory. If space is not available it must wait until the packet fetched
by the MAC completes transmission and is subsequently removed from the packet buffer memory.
Note that if full store and forward mode is active, and if a single frame is fetched that is too large for
the packet buffer memory, the frame is flushed and the DMA is halted with an error status. This is
because a complete frame must be written into the packet buffer before transmission can begin, and
therefore the minimum packet buffer memory size should be chosen to satisfy the maximum frame
to be transmitted in the application.
When the complete transmit frame is written into the packet buffer memory, a trigger is sent across
to the MAC transmitter, which then begins reading the frame from the packet buffer memory.
Because the whole frame is present and stable in the packet buffer memory, an underflow of the
transmitter is not possible. The frame is kept in the packet buffer until notification is received from
the MAC that the frame data has either been successfully transmitted or can no longer be
re-transmitted (too many retries in half duplex mode). When this notification is received the frame is
flushed from memory to make room for a new frame to be fetched from AHB system memory.
In half duplex mode, the frame is kept in the packet buffer until notification is received from the MAC
that the frame data has either been successfully transmitted or can no longer be re-transmitted (too
many retries in half duplex mode). When this notification is received the frame is flushed from
memory to make room for a new frame to be fetched from AHB system memory.
In full duplex mode, the frame is removed from the packet buffer on-the-fly.