User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 499
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Rx Checksum Offload
When receive checksum offloading is enabled, the IPv4 header checksum is checked per RFC 791,
where the packet meets the following criteria:
• If present, the VLAN header must be four octets long and the CFI bit must not be set
• Encapsulation must be RFC 894 Ethernet Type encoding or RFC 1042 SNAP encoding
•IPv4 packet
• IP header is of a valid length
The controller also checks the TCP checksum per RFC 793, or the UDP checksum per RFC 768, if the
following criteria are met:
•IPv4 or IPv6 packet
• Good IP header checksum (if IPv4)
•No IP fragmentation
•TCP or UDP packet
When an IP, TCP, or UDP frame is received, the receive buffer descriptor provides an indication if the
controller was able to verify the checksums. There is also an indication if the frame had LLC SNAP
encapsulation. These indication bits replace the type ID match indication bits when receive checksum
offload is enabled.
If any of the checksums are verified to be incorrect by the controller, the packet is discarded and the
appropriate statistics counter is incremented.
Tx Checksum Offload
The transmitter checksum offload is only available when the full store and forward mode is enabled.
This is because the complete frame to be transmitted must be read into the packet buffer memory
before the checksum can be calculated and written back into the headers at the beginning of the
frame.
Transmitter checksum offload is enabled by setting bit [11] in the DMA Configuration register. When
enabled, it monitors the frame as it is written into the transmitter packet buffer memory to
automatically detect the protocol of the frame. Protocol support is identical to the receiver checksum
offload.
For transmit checksum generation and substitution to occur, the protocol of the frame must be
recognized and the frame must be provided without the FCS field, by ensuring that bit [16] of the
transmit descriptor word 1 is clear. If the frame data already had the FCS field, this would be
corrupted by the substitution of the new checksum fields.
If these conditions are met, the transmit checksum offload engine calculates the IP, TCP, and UDP
checksums as appropriate. When the full packet is completely written into packet buffer memory, the
checksums are valid and the relevant DPRAM locations are updated for the new checksum fields as
per standard IP/TCP and UDP packet structures.