User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 50
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
2.5.3 MIO Pin Assignment Considerations
Normally, each pin is assigned to one function. One exception to this is the dual use boot mode
strapping resistors (MIO [2:8]).
IMPORTANT: There are several important MIO pin assignment considerations. The MIO-at-a-Glance
table, the interface routing table, and these pin assignment considerations are helpful when doing pin
planning.
Interface Frequencies: The clocking frequency for an interface usually depends on device speed
grade and whether the interface is routed via MIO or EMIO. The possible routing paths for each
interface are listed in Table 2-3, page 48. The maximum clock frequency that can be used for each
speed grade and routing path are defined in the Zynq-7000 AP SoC data sheets.
Two MIO Voltage Banks: The MIO pins are split across two independently configured sets of I/O
buffers: Bank 0, MIO[15:0] and Bank 1, MIO[53:16]. The signalling voltage is initially configured using
the VMODE boot mode strapping pins. Each bank can be configure for 1.8V signalling or 2.5V/3.3V.
Boot Mode Strapping Pins: These pins can be assigned to I/O peripherals in addition to functioning
as boot mode pins. MIO pins [8:2], define the boot device, the initial PLL clock bypass mode, and the
voltage mode (VMODE) for the MIO banks. The strapping pins are sampled a few PS_CLK clock cycles
after the PS_POR_B reset signal de-asserts. The board design ties these signals to VCC or ground
using 20 KΩ pull-up and pull-down resisters. More information about the boot mode pin settings is
provided in
Chapter 6, Boot and Configuration.
I/O Buffer Output Enable Control: The output enable for each MIO I/O buffer is controlled by a
combination of the setting of the three-state override control bit, the selected signal type (input-only
or not), and the state of the peripheral controller. The three-state override bit can be controlled from
either of two places: the slcr.MIO_PIN_xx [TRI_ENABLE] register bit or the slcr.MIO_MST_TRI register
bits. These bits control the same flip-flop to help control the three-state signal of the I/O buffer. The
I/O buffer output is enabled when the three-state override control bit = 0 and either the signal is an
output-only or the I/O peripheral desires to drive a signal that is configured as I/O.
Boot from SD Card: The BootROM expects the SD card to be connected to MIO pins 40 through 45
(SDIO 0 interface).
Static Memory Controller (SMC) Interface: Only one SMC memory interface can be used in a
design. The SMC controller consumes many of the MIO pins and neither of the SMC memory
interfaces can be routed to the EMIO.
For example, if an 8-bit NAND Flash is implemented, then Quad-SPI, is not available and the test port
is limited to 8-bits. If a 16-bit NAND Flash is implemented, then additional pins are consumed.
Ethernet 0 is not available. The SRAM/NOR interface consumes up to 70% of the MIO pins,
eliminating Ethernet and USB 0.
The SRAM/NOR upper address pins are optional, as appropriate for the attached device. Also note
that the SMC interface straddles the two MIO voltage banks.