User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 500
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20]
of the transmitter DMA writeback status are updated to identify the reason for the error. Note that
the frame is still transmitted but without the checksum substitution, as typically the reason that the
substitution did not occur was that the protocol was not recognized.
16.2.7 IEEE 1588 Time Stamp Unit
IEEE 1588 is a standard for precision time synchronization in local area networks. It works with the
exchange of special precision time protocol (PTP) frames. The PTP messages can be transported over
IEEE 802.3/Ethernet, over Internet Protocol Version 4 or over Internet Protocol Version 6 as described
in the annex of IEEE P1588.D2.1.
The controller detects when the PTP event messages sync, delay_req, pdelay_req and pdelay_resp are
transmitted and received.
Synchronization between master and slave clocks is a two stage process.
• First, the offset between the master and slave clocks is corrected by the master sending a sync
frame to the slave with a follow up frame containing the exact time the sync frame was sent.
Hardware assist modules at the master and slave side detect exactly when the sync frame was
sent by the master and received by the slave. The slave then corrects its clock to match the
master clock.
• Second, the transmission delay between the master and slave is corrected. The slave sends a
delay request frame to the master which sends a delay response frame in reply. Hardware assist
modules at the master and slave side detect exactly when the delay request frame was sent by
the slave and received by the master. The slave then has enough information to adjust its clock
to account for delay. For example, if the slave was assuming zero delay the actual delay is half
the difference between the transmit and receive time of the delay request frame (assuming
equal transmit and receive times) because the slave clock is lagging the master clock by the
delay time already.
For hardware assist it is necessary to timestamp when sync and delay_req messages are sent and
received. The timestamp is taken when the message timestamp point passes the clock timestamp
point. The message timestamp point is the SFD and the clock timestamp point is the MII interface.
(The 1588 spec refers to sync and delay_req messages as event messages as these require
timestamping. Follow up, delay response and management messages do not require timestamping
and are referred to as general messages.)
1588 version 2 defines two additional PTP event messages. These are the peer delay request
(Pdelay_Req) and peer delay response (Pdelay_Resp) messages. These messages are used to calculate
the delay on a link. Nodes at both ends of a link send both types of frames (regardless of whether
they contain a master or slave clock). The Pdelay_Resp message contains the time at which a
Pdelay_Req was received and is itself an event message. The time at which a Pdelay_Resp message is
received is returned in a Pdelay_Resp_Follow_Up message.
The controller recognizes four different encapsulations for PTP event messages:
• 1588 version 1 (UDP/IPv4 multicast)
• 1588 version 2 (UDP/IPv4 multicast)
• 1588 version 2 (UDP/IPv6 multicast)