User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 501
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
• 1588 version 2 (Ethernet multicast)
Note: Only multicast packets are supported.
The TSU consists of a timer and registers to capture the time at which PTP event frames cross the
message timestamp point. These are accessible through the APB interface. An interrupt is issued
when a capture register is updated.
The MAC provides timestamp registers that capture the departure time (for transmit) or arrival time
(for receive) of PTP event packets (sync and delay request) and peer event packets (peer delay
request or peer delay response). Interrupts are optionally generated upon timestamp capture.
The MAC also provides an option to timestamp all received packets by replacing the packet's FCS
word with the nanoseconds portion of the timestamp. This eliminates the need to respond to
received timestamp interrupts and to associate the timestamps with the correct received packets.
The timestamp unit includes a 62-bit timer counter. The lower 30 bits count nanoseconds and the
upper 32 bits count seconds. Every clock cycle the counter is incremented by a programmable
number of nanoseconds, and a mechanism is provided to handle fractional values. For example, at
120 MHz, the clock period is 8.333 ns. Every 3 clock cycles the counter is incremented twice by 8 and
once by 9, for an average increment of 8.333 ns. The counter is clocked by the CPU 1x which is
derived from the CPU clock.
There are six additional registers that capture the time at which PTP event frames are transmitted
and received. An interrupt is issued when these registers are updated.
IEEE 1588 Limitations
These topics can be addressed by software, but the added software workload limits the capabilities
and accuracy of the IEEE1588 support. In many non-real-time operating systems, the interrupt
response time is long, making it more difficult to achieve high accuracy.
Time Counter Clock Input
The 62-bit time counter is clocked by the CPU_1x clock and there is no option for a separate clock
input. Thus the choice of clock frequency and precision is related to the CPU clock frequency.
62-bit Time Counter Accuracy
The counter accuracy is limited to 62 bits. The least significant bits are in nanosecond units, and
there is no direct support for counting fractions of nanoseconds. A mechanism is provided to allow
fractional increments by averaging between two integer values, but its accuracy is limited and it
creates jitter of up to ±128 ns.
Counter Value to the PL
The 62-bit counter value is only accessible by reading a register. It is therefore not directly possible
to schedule hardware events upon the counter reaching a specific value.