User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 503
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
with its timestamp (for both transmit and receive), and make it available to software, for example via
FIFOs or via circular buffers in main memory. Such a function can be implemented in the PL along
with the timestamp unit as described above.
However, implementation requires access to the packet data stream itself. In order to have access to
the packet data stream, the controller needs to be pinned-out through the EMIO using GMII, instead
of MIO. By selecting this option, the GMII signals are exposed to the PL and can be used to detect
and capture the PTP packets. Note that it is still possible to use the PTP frame recognition in the
MAC, or it is possible to design this function in the PL as well (e.g., if support for unicast packets is
required).
16.2.8 MAC 802.3 Pause Frame Support
Note: See Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description of
pause operation.
The start of an 802.3 pause frame is shown in Table 16-4
The controller supports both hardware controlled pause of the transmitter upon reception of a pause
frame and hardware generated pause frame transmission.
802.3 Pause Frame Reception
Bit [13] of the Network Configuration register is the pause enable control for reception. If this bit is
set transmission pauses if a non zero pause quantum frame is received.
If a valid pause frame is received then the pause time register is updated with the new frame's pause
time regardless of whether a previous pause frame is active or not. An interrupt (either bit [12] or bit
[13] of the Interrupt Status register) is triggered when a pause frame is received, but only if the
interrupt has been enabled (bit [12] and bit [13] of the Interrupt Mask register). Pause frames
received with non zero quantum are indicated through the interrupt bit [12] of the Interrupt Status
register. Pause frames received with zero quantum are indicated on bit [13] of the Interrupt Status
register.
When the pause time register is loaded and the frame currently being transmitted has been sent, no
new frames are transmitted until the pause time reaches zero. The loading of a new pause time, and
hence the pausing of transmission, only occurs when the controller is configured for full duplex
operation. If the controller is configured for half duplex there is no transmission pause, but the pause
frame received interrupt is still triggered. A valid pause frame is defined as having a destination
address that matches either the address stored in Specific Address register 1 or if it matches the
reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808
and have the pause opcode of 0x0001.
Table 16-4: Pause Frame Information
Destination Address Source Address
Type
(MAC Control Frame)
Pause Opcode Pause Time
0x0180C2000001
6 bytes
0x8808 0x0001
2 bytes