User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 504
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Pause frames that have FCS or other errors are treated as invalid and are discarded. 802.3 Pause
frames that are received after priority based flow control (PFC) has been negotiated are also
discarded. Valid pause frames received increment the Pause Frames Received Statistic register.
The Pause Time register decrements every 512 bit times once transmission has stopped. For test
purposes, the retry test bit can be set (bit [12] in the Network Configuration register) which causes
the Pause Time register to decrement every tx_clk cycle when transmission has stopped.
The interrupt (bit [13] in the Interrupt Status register) is asserted whenever the pause time register
decrements to zero (assuming it has been enabled by bit [13] in the Interrupt Mask register). This
interrupt is also set when a zero quantum pause frame is received.
802.3 Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit pause frame bits of the
Network Control register and from the external input pins tx_pause, tx_pause_zero and tx_pfc_sel. If
either bit [11] or bit [12] of the Network Control register is written with logic 1, or if the input signal
tx_pause is toggled when tx_pfc_sel is Low, an 802.3 pause frame is transmitted providing full duplex
is selected in the Network Configuration register and the transmit block is enabled in the Network
Control register.
Pause frame transmission occurs immediately if transmit is inactive or if transmit is active between
the current frame and the next frame due to be transmitted.
Transmitted pause frames comprise of the following:
• A destination address of 01-80-C2-00-00-01
• A source address taken from Specific Address register 1
•A type ID of 88-08 (MAC control frame)
• A pause opcode of 00-01
• A pause quantum register
• Fill of 00 to take the frame to minimum frame length
•Valid FCS
The pause quantum used in the generated frame depends on the trigger source for the frame as
follows:
• If bit [11] is written with a one, the pause quantum is taken from the Transmit Pause Quantum
register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum
pause quantum as the default.
• If bit [12] is written with a one, the pause quantum is zero.
• If the tx_pause input is toggled, tx_pfc_sel is Low and the tx_pause_zero input is held Low until
the next toggle, the pause quantum is taken from the Transmit Pause Quantum register.
• If the tx_pause input is toggled, tx_pfc_sel is Low and the tx_pause_zero input is held High until
the next toggle, the pause quantum is zero.
After transmission, a pause frame transmitted interrupt is generated (bit [14] of the Interrupt Status
register) and the only statistics register that is incremented is the Pause Frames Transmitted register.