User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 505
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Pause frames can also be transmitted by the MAC using normal frame transmission methods.
MAC PFC Priority Based Pause Frame Support
Note: Refer to the 802.1Qbb standard for a full description of priority based pause operation.
The controller supports PFC priority based pause transmission and reception. Before PFC pause
frames can be received, bit 16 of the Network Control register must be set. The start of a PFC pause
frame is shown in Table 16-5.
PFC Pause Frame Reception
The ability to receive and decode priority based pause frames is enabled by setting bit [16] of the
Network Control register. When this bit is set, the controller matches either classic 802.3 pause
frames or PFC priority based pause frames. Once a priority based pause frame has been received and
matched, then from that moment on the controller only matches on priority based pause frames (this
is an 802.1Qbb requirement, known as PFC negotiation). Once priority based pause has been
negotiated, any received 802.3x format pause frames are not acted upon. The state of PFC
negotiation is identified via the output pfc_negotiate.
If a valid priority based pause frame is received then the controller decodes the frame and
determines which, if any, of the eight priorities require to be paused. Up to eight Pause Time
registers are then updated with the eight pause times extracted from the frame, regardless of
whether a previous pause operation is active or not. An interrupt (either bit [12] or bit [13] of the
Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has
been enabled (via bit[12] and bit[13] of the Interrupt Mask register).
Pause frames received with non zero quantum are indicated through the interrupt bit[12] of the
Interrupt Status register. Pause frames received with zero quanta are indicated on bit[13] of the
Interrupt Status register. The state of the eight pause time counters are indicated through the
outputs rx_pfc_paused. These outputs remain High for the duration of the pause time quanta. The
loading of a new pause time only occurs when the controller is configured for full duplex operation.
If the controller is configured for half duplex, the pause time counters are not loaded, but the pause
frame received interrupt is still triggered.
A valid pause frame is defined as having a destination address that matches either the address
stored in Specific Address register 1 or if it matches the reserved address of 0x0180C2000001. It
must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0101.
Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause
frames received increment the pause Frames Received Statistic register.
The Pause Time registers decrement every 512 bit times immediately following the PFC frame
reception. For test purposes, the retry test bit can be set (bit [12] in the Network Configuration
Table 16-5: PFC Priority Based Pause Frame Info
Destination Address Source Address
Type
(MAC Control Frame)
Pause
Opcode
Priority
Enable Vector
Pause
Times
0x0180C2000001
6 bytes
0x8808 0x0101
2 bytes 8 * 2 bytes