User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 506
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
register) which causes the Pause Time register to decrement every rx_clk cycle once transmission has
stopped.
The interrupt (bit [13] in the Interrupt Status register) is asserted whenever the Pause Time register
decrements to zero (assuming it has been enabled by bit [13] in the Interrupt Mask register). This
interrupt is also set when a zero quantum pause frame is received.
PFC Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit priority based pause
frame bit of the Network Control register and from the external input pins tx_pause,
tx_pfc_pause[7:0], tx_pfc_pause_zero[7:0], and tx_pfc_sel. If bit 17 of the Network Control register is
written with logic 1, or if the input signal tx_pause is toggled when tx_pfc_sel is High, a PFC pause
frame is transmitted providing full duplex is selected in the Network Configuration register and the
transmit block is enabled in the Network Control register. When bit 17 of the Network Control
register is set, the fields of the priority based pause frame are built using the values stored in the
Transmit PFC Pause register.
Pause frame transmission occurs immediately if transmit is inactive or if transmit is active between
the current frame and the next frame due to be transmitted.
Transmitted pause frames comprise of the following:
• A destination address of 01-80-C2-00-00-01
• A source address taken from Specific Address register 1
•A type ID of 88-08 (MAC control frame)
• A pause opcode of 01-01
• A priority enable vector taken from tx_pfc_pause or the Transmit PFC Pause register
• Eight pause quantum registers
• Fill of 00 to take the frame to minimum frame length
•Valid FCS
The Pause Quantum registers used in the generated frame depend on the trigger source for the
frame as follows:
• If bit [17] of the Network Control register is written with a one then the priority enable vector of
the priority based pause frame is set equal to the value stored in the Transmit PFC Pause register
[7:0]. For each entry equal to zero in the Transmit PFC Pause register[15:8], the pause quantum
field of the pause frame associated with that entry is taken from the Transmit Pause Quantum
register. For each entry equal to one in the Transmit PFC Pause register[15:8], the pause
quantum associated with that entry is zero.
• The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause
quantum as default.
• If the tx_pause input is toggled and tx_pfc_sel is High then the priority enable vector of the
priority based pause frame is set equal to the value in tx_pfc_pause [7:0]. For each entry equal to
zero in tx_pfc_pause_zero[7:0], the pause quantum field of the pause frame associated with that
entry is taken from the Transmit Pause Quantum register. For each entry equal to one in
tx_pfc_pause_zero [7:0], the pause quantum associated with that entry is zero.