User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 508
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
16.3.2 Configure the Controller
The following example describes a typical programming sequence for configuration of the controller.
Refer to Appendix B, Register Details for further details on the Controller registers.
1. Program the Network Configuration register (gem.net_cfg). The network configuration
register is used to set the mode of operation.
Examples:
a. Enable Full Duplex. Write a 1 to the gem.net_cfg[full_duplex] register.
b. Enable Gigabit mode. Write a 1 to the gem.net_cfg[gige_en] register.
c. Enable default speed for 100 Mbps. Write a 1 to the gem.net_cfg[speed] register.
Note: The speed bit might have to be re-written after PHY auto-negotiation.
d. Enable reception of broadcast or multicast frames. Write a 0 to the
gem.net_cfg[no_broadcast] register to enable broadcast frames and write a 1 to the
gem.net_cfg[multi_hash_en] register to enable multicast frames.
e. Enable promiscuous mode. Write a 1 to the gem.net_cfg[copy_all] register.
f. Enable TCP/IP checksum offload feature on receive. Write a 1 to the
gem.net_cfg[rx_chksum_offld_en] register. (Refer to section 16.2.6 Checksum Offloading.)
g. Enable Pause frames. Write a 1 to gem.net_cfg[pause_en] register.
h. Set the MDC clock divisor. Write the appropriate MDC clock divisor to the
gem.net_cfg[mdc_clk_div] register. (Refer to section 16.3.4 Configure the PHY.)
2. Set the MAC address. Write to the gem.spec1_addr1_bot and gem.spec1_addr1_top registers.
The least significant 32 bits of the MAC address go to gem.spec1_addr1_bot and the most
significant 16 bits go to gem.spec1_addr1_top.
3. Program the DMA Configuration register (gem.dma_cfg).
a. Set the receive buffer size to 1,600 bytes. Write a value of 0x19 to the
gem.dma_cfg[ahb_mem_rx_buf_size] register.
b. Set the receiver packet buffer memory size to the full configured addressable space of
8KB. Write 0x3 to the gem.dma_cfg[rx_pktbuf_memsz_sel] register.
c. Set the transmitter packet buffer memory size to the full configured addressable space
of 4 KB. Write 0x1 to the gem.dma_cfg[tx_pktbuf_memsz_sel] register.
d. Enable TCP/IP checksum generation offload on the transmitter. Write 0x1 to the
gem.dma_cfg[csum_gen_offload_en] register.
e. Configure for Little Endian system. Write 0x0 to the
gem.dma_cfg[ahb_endian_swp_pkt_en] register.
f. Configure AHB fixed burst length. Write 0x10 to the gem.dma_cfg[ahb_fixed_burst_len]
register to use INCR16 AHB burst for higher performance.
4. Program the Network Control Register (gem.net_ctrl).
a. Enable MDIO. Write a 1 to the gem.net_ctrl[mgmt_port_en] register.
b. Enable the Transmitter. Write a 1 to the gem.net_ctrl[tx_en] register.
c.
Enable the Receiver. Write a 1 to
the gem.net_ctrl[rx_en] register.