User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 511
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
The MDC must not exceed 2.5 MHz as defined by the IEEE802.3 standard. The
gem.net_cfg[mdc_clk_div] bits are used to set the divisor for the CPU_1x clock.
Example: Consider a case with the CPU clock set to 666.667 MHz clock and the available CPU_1x
clock is 111.11 MHz. The clock divisor, in this case should be set to 48 (0b011) in
gem.net_cfg[mdc_clk_div] to set the maximum possible frequency of 2.314 MHz for the MDC.
PHY configuration and initialization is unique for every system. Refer to the vendor data sheet for
more information and PHY register details.
Example: PHY Read/Write Operation
1. Check to see that no MDIO operation is in progress. Read until
gem.net_status[phy_mgmt_idle] = 1.
2. Write data to the PHY maintenance register(gem.phy_maint). This initiates the shift
operation over MDIO. Refer to Appendix B, Register Details section B.18 Gigabit Ethernet
Controller (GEM)for register information.
3. Wait for completion of operation. Read until gem.net_statusp[phy_mgmt_idle] = 1.
4. Read data bits for a read operation. The PHY register data is available in gem.phy_maint[data].
Example: PHY Initialization
1. Detect the PHY address. Read the PHY identifier fields in PHY registers 2 and 3 for all the PHY
addresses ranging from 1 to 32. The register contents will be valid for a valid PHY address.
2. Advertise the relevant speed/duplex settings. These bits can be set to suit the system. Refer to
the PHY vendor data sheet for more information.
3. Configure the PHY as applicable. This could include options to set PHY mode, timing options
in the PHY or others as applicable to the system. Refer to the PHY vendor datasheet for more
information.
4. Wait for completion of Auto-negotiation. Read the PHY status register. Refer to the PHY
vendor data sheet for more information.
5. Update Controller with auto-negotiated speed and duplex settings. Read the relevant PHY
registers to determine the negotiated speed and duplex. Set the speed in gem.net_cfg[gige_en]
and gem.net_cfg[speed] bits and the duplex in gem.net_cfg[full_duplex].
Note: The SLCR register must be updated for clock updates (refer to Configure Clocks, page 510).
16.3.5 Configure the Buffer Descriptors
Receive Buffer Descriptor List
The data received by the controller is written to pre-allocated buffer descriptors in system memory.
These buffer descriptor entries are listed in the receive buffer queue. Refer to section 16.2.5 DMA
Block and Table 16-2, page 489 for more information on implementation and structure of the Rx
Buffer Descriptor.
The Receive-buffer Queue Pointer register (gem.rx_qbar) points to this data structure as shown in
Figure 16-4.