User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 513
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
The Transmit Buffer Queue Pointer register (gem.tx_qbar) register points to this data structure.
To create this list of buffer descriptors with N entries:
1. Each buffer descriptor is 8 bytes in length. Hence allocate an area of 8N bytes for the transmit
buffer descriptor list in system memory which creates N entries in this list. It is advisable to use
un-cached memory for allocating the complete buffer descriptor list for the reasons already
described for the Receive Buffer Descriptor List.
2. Mark all entries in this list as owned by the controller. Set bit[31] of word 1 to 0.
3. Mark the last descriptor in the list with the wrap bit. Set bit[30] in word 1 to 1.
4. Write the base address of transmit buffer descriptor list to Controller register gem.tx_qbar.
16.3.6 Configure Interrupts
There are 26 interrupt conditions that are detected within the controller which are OR-ed to generate
a single interrupt. Additionally there is a Wake-on-LAN interrupt driven from the Ethernet controller.
These two interrupts are then passed to the GIC pl390 interrupt controller.
Refer to the description of register, gem.intr_status in Appendix B, Register Details for more
information on the list of interrupt conditions identified by the controller.
An appropriate handler for the interrupt should be registered with the CPU for processing an
interrupt condition. The CPU suspends its normal activity, moves to interrupt processing mode and
executes the corresponding handler for an interrupt condition.
Example: Configuring Interrupts
1. Register a handler. There are two interrupts generated by the controller - Wake-on-LAN and
another interrupt for all other functions. Register the handler for each of these interrupt types
with the CPU.
Note: In a typical case, a single handler is used for both transmission and reception of packets.
Once the control reaches the handler, the software should read the gem.intr_status register to
determine the source and perform the relevant function.
2. Enable the necessary interrupt conditions. The relevant bits in the gem.intr_en register must
be set. The interrupt conditions necessary are determined by the system architecture.
Note: Read the read-only register gem.intr_mask for current the mask state of each interrupt.
16.3.7 Enable the Controller
The receiver and transmitter must be enabled after configuration:
1. Enable the Transmitter. Write a 1 to gem.net_ctrl[tx_en].
2. Enable the Receiver. Write a 1 to gem.net_ctrl[rx_en].