User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 514
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
16.3.8 Transmitting Frames
Example: Transmitting a Frame
1. Allocate buffers in system memory to contain the Ethernet frame. GigE supports
scatter-gather functionality; hence an Ethernet frame can be split into multiple buffers with each
buffer processed by a buffer descriptor.
2. Write the Ethernet frame data in the allocated buffers. These Ethernet frames should have
their header fields such as destination MAC address, source MAC address and type/length field
set appropriately.
Notes:
°
The FCS field is added by the MAC in most cases. However if there is a need to append a
custom FCS, bit 16 in word 1 of the corresponding buffer descriptor must be set.
°
The buffer that contains the Ethernet frame data should be flushed from cache if cached
memory is being used.
3. Allocate buffer descriptor(s) for the Ethernet frame buffers. This involves setting bits 0-31 in
the buffer descriptor word 0 with the address of the buffer and setting bits 0-13 in word 1 with
the length of the buffer to be transmitted.
Notes:
°
For single buffer Ethernet frames, bit 15 (Last buffer bit) of the word 1 must also be set.
°
For Ethernet frames scattered across multiple buffers the buffer descriptors must be
allocated serially and the buffer descriptor containing the last buffer should have the bit 15
of word 1 set.
Example: For an Ethernet frame of 1,000 bytes split across two buffers with the first buffer
containing the Ethernet header (14 bytes) and the next buffer containing the remaining 986
bytes, the buffer descriptor with index N should be allocated for the first buffer and the buffer
descriptor with index N+1 should be allocated for the second buffer. Bit 15 of word 1 of the N+1
buffer descriptor must also be set to mark it as the last buffer in the scattered list of Ethernet
frames.
4. Clear the used bit (bit 31) in the word 1 of the allocated buffer descriptors.
5. Enable transmission. Write a 1 to gem.net_ctrl[start_tx].
6. Wait until the transmission is complete. An interrupt is generated by the controller upon
successful completion of the transmission. Read and clear the gem.intr_status[tx_complete] bit
by writing a 1 to the bit In the interrupt handler. Also read and clear the gem.tx_status register by
writing a 1 to gem.tx_status[tx_complete] bit. Clear all bits in the BD except the used and wrap
bits.
16.3.9 Receiving Frames
When a frame is received with the receive circuits enabled, the controller checks the address and the
frame is written to system memory in the following cases:
• The destination address matches one of the four specific address registers. This is applicable for
cases where the MAC address for the controller is set in thr gem.spec_addr{1:4}_bot and
gem.spec_addr{1:4}_top registers.