User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 515
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
• The received frame's type/length field matches one of the four type ID registers. The available
type id registers are gem.type_id_match{1:4}. This is applicable for cases where Ethernet
type/length field based filtering is required.
• Unicast or Multicast hash is enabled through gem.net_cfg[uni_hash_en] or
gem.net_cfg[multi_hash_en] register bits, then the received frame is accepted only if the hash is
matched.
• The destination address is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
This option is set using the gem.net_cfg[no_broadcast] register bit.
• The controller is configured for promiscuous mode with the gem.net_cfg[copy_all] register bit
set.
The register gem.rx_qbar points to the next entry in the receive buffer descriptor list and the
controller uses this as the address in system memory to write the frame. When the frame has been
completely received and written to system memory, the controller then updates the receive buffer
descriptor entry with the reason for the address match, marks the area as being owned by software,
and sets the receive complete interrupt (gem.intr_status[rx_complete] = 1). Software is then
responsible for copying the data to the application area and releasing the buffer.
If the controller is unable to write the data at a rate to match the incoming frame, then the receiver
overrun interrupt is set (gem.intr_status[rx_overrun] = 1). If there is no receive buffer available, i.e.,
the next buffer is still owned by software, a receive-buffer not available interrupt is set. If the frame
is not successfully received, a Statistic register is incremented and the frame is discarded without
informing software.
Example: Handling a Received Frame
1. Wait for the controller to receive a frame. The receive complete interrupt,
gem.intr_status[rx_complete], is generated when a frame is received.
2. Service the interrupt. Read and clear the gem.intr_status[rx_complete] register bit writing a 1 to
the bit in the interrupt handler. Also read and clear the gem.rx_status register by writing a 1 to
gem.rx_status[frame_recd] bit.
3. Process the data in the buffer. Scan the buffer descriptor list for the buffer descriptors with the
ownership bit (bit 0, Word 0) set. When the DMA receive buffer size programmed to 1,600 bytes
(gem.dma_cfg[ahb_mem_rx_buf_size] = 0x19), the packets on the receive side are not scattered
and always go into a single buffer. For a buffer descriptor with the ownership bit set, process the
buffer allocated in the corresponding buffer descriptor and set the ownership bit to 0. Read
other bit fields in the relevant buffer descriptor word 1, take necessary action, and clear them.
16.3.10 Debug Guide
The GigE can encounter different kinds of errors while receiving or transmitting Ethernet frames.
Refer to Appendix B, Register Details for more information on the transmit and receive error
conditions listed in the description for gem.tx_status and gem.rx_status registers, respectively.
Some common errors and the action necessary is described in Table 16-6 and Table 16-7.