User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 516
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Table 16-6: RX Status Errors
Error Condition Necessary Action
Hresp not OK This is a condition from which the controller cannot recover easily. Re-initialize the
controller and buffer descriptors for receive and transmit paths after clearing the
relevant register status bits: gem.rx_status[hresp_not_ok] and
gem.intr_status[hresp_not_ok].
Receive overrun This condition implies that the packet is dropped because the packet buffer is full and
occurs occasionally when the controller is unable to process the packets when they
arrive very fast. In most conditions, no action for error recovery needs to be taken.
Ensure that the packet buffer is configured for 8 KB (see section 16.3.2 Configure the
Controller) and clear bits gem.rx_status[rx_overrun] and gem.intr_status[rx_overrun].
Buffer not available This condition implies that the controller could not get a buffer descriptor with the
ownership bit set to 0. It can also mean that the software is unable to keep pace with
the incoming packet rate. Clear bits gem.rx_status[buffer_not_avail] and
gem.intr_status[rx_used_read] in the interrupt handler. Attempt increasing the number
of buffer descriptors on the receive path to allocate more number of buffers. The
software processing can be optimized further to accelerate processing of received
frames.
Table 16-7: TX Status Errors
Error Condition Necessary Action
Hresp not OK This is a condition from which the controller cannot recover easily. Re-initialize the
controller and buffer descriptors for receive and transmit paths after clearing the
relevant register status bits: gem.tx_status[hresp_not_ok] and
gem.intr_status[hresp_not_ok].
Transmit underrun This implies a severe error condition on the transmit side in processing of the transmit
buffers and buffer descriptors. For effective error recovery, the software must disable
the transmitter by writing a 0 to the gem.net_ctrl[tx_en] bit, then re-initialize the buffer
descriptors on the transmit side and enable the transmitter by writing a 1 to the
gem.net_ctrl[tx_en] bit. The bit gem.tx_status[tx_under_run] must be cleared in the
interrupt handler.
Transmit buffer
exhausted
This is a severe error condition on the transmit side. For effective error recovery, the
software must disable the transmitter by writing a a 0 to the gem.net_ctrl[tx_en] bit,
then re-initialize the transmit buffer descriptors and transmitter. The register bits
gem.tx_status[tx_corr_ahb_err] and gem.intr_status[tx_corrupt_ahb_err] must be
cleared in the interrupt handler.
Retry limit exceeded This implies there are a series of collisions for which an Ethernet frame could not be
sent out even with a number of retries in half-duplex communication. This Ethernet
frames are dropped at the transmitter. The bits gem.tx_status[retry_limit_exceeded]
and gem.intr_status[retry_ex_late_collisn]must be cleared in the interrupt handler. No
drastic measures need to be taken for this error. However it could also mean that there
is a duplex setting mismatch.
Collisions This error indicates that there are collisions for half duplex communication. Some
collisions are expected in half duplex mode and can be ignored. When a collision
occurs, the frame is retransmitted after a while and the frame is not dropped. The
register bit gem.tx_status[collision] must be cleared in the interrupt handler.