User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 517
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
16.4 IEEE 1588 Time Stamping
16.4.1 Overview
Refer to the IEEE 1588 standard specification for more information on the protocol and section
16.2.7 IEEE 1588 Time Stamp Unit for more information on the implementation of the Timestamp
Unit. The following section briefly reviews the essential terms prior to discussion of the programming
model.
The PTP system deals with the following different entities:
• A grandmaster clock. This is typically the IEEE1588 master clock which is the ultimate source of
time on the network.
• A boundary clock. It is a multi-port switch containing one port that is a PTP slave to a master
clock, while the other ports are masters to downstream slave clocks.
• A transparent clock. This is a PTP enhanced switch which modifies the precise time stamps
within relevant PTP packets to account for transmit and receive delays within the individual
switch itself.
• An ordinary clock. This is the typical PTP client.
For more information on different types of PTP clocks refer to the IEEE1588-2008 standard
specification.
Synchronization and management of a PTP system is achieved through the exchange of messages
across the network. PTP uses the following message types:
• Sync, Delay_Req, Follow_up, and Delay_Resp messages are used by ordinary and boundary
clocks. They are used to communicate timing information for clock synchronization.
• Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up are used to measure path delays across
the communication medium so that they can be compensated for by the system. These are
extensively used by transparent clocks and are available only in PTPv2.
• Announce messages are used by best master clock algorithm (BMCA) to build a clock hierarchy
and select the grandmaster clock.
• Management messages are used for network monitoring and management.
• Signaling frames are used for non -time critical communication across clocks.
Refer to IEEE1588-2008 Clause 13 for more information on message types and formats.
PTP Message Format
All PTP messages contain a header, body and suffix. The PTP message header is 34 bytes long. Please
refer to IEEE1588-2008 Clause 13 for more information on message formats. The important fields in
the message header are described briefly as follows:
• Each clock port is identified by Source Port Identity (sourcePortIdentity) which is a 10 byte
address. The sourcePortIdentity is common for all PTP messages.