User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 519
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
2. Best master clock algorithm (BMCA)
3. PTP packet handling at the master port
4. PTP packet handling at the slave port
Notes:
1. The following sections do not describe the handling of management and signaling frames
because they are not integral to the implementation of the core PTP functionality.
2. The illustrations in these sections do not describe an implementation-specific mechanism to
change clock attributes dynamically.
3. The PTP packets processed here are simple Ethernet multicast packets. The scope of the
following sections do not include UDP based multicast packets. The explanation refers to non-OS
based standalone implementation which does not implement a TCP/IP stack.
16.4.2 Controller Initialization
The controller must be initialized with the interrupts, timer and PTP.
1. Initialize the controller with interrupts and timers. Refer to section 16.3 Programming Guide.
2. Enable the PTP interrupts. Refer to section 16.3.6 Configure Interrupts
3. Setup a timer with interrupts and appropriate interrupt handlers to enable periodic
transmission of packets. TTC timers or CPU private timers can be used for this purpose. For a
typical case, interrupts can be generated every 500 ms.
4. Setup the UART to monitor debug messages from the application. Refer to Chapter 19, UART
Controller to program the UART.
The following steps are specifically for the PTP functionality:
1. Initialize the seconds and nanoseconds timers. Write appropriate values to the gem.timer_s
and gem.timer_ns registers, respectively.
2. Program the timer increment value in the gem.timer_incr register.
Example: For a CPU clock that runs at 666.67 MHz and PTP clocked with CPU_1x clock of
111.11 MHz, 1 PTP clock cycle corresponds to 9 ns. The gem.timer_incr[ns_delta] register bit in
this case should be set to 9.
As another example, consider a CPU_1x clock of 120 MHz, 1 PTP clock cycle corresponds to
8.33 ns. In this case, the counter should increment by 8 ns for 2 clock cycles and 9 ns for 1 clock
cycle to average 8.33 ns in 3 clock cycles. For such a setting, register bit gem.timer_incr[ns_delta]
is set to 8, gem.timer_incr[alt_ct_ns_delta] is set to 9, and gem.timer_incr[incr_b4_alt] is set to 2.
3. Initialize the common fields of data structures used for various PTP packets. All PTP packets
have a common message header.
Timer Interrupt Handler
A timer is initialized to generate interrupts at pre-defined intervals. The operation of the interrupt
handler at the master and slave clock ports are briefly illustrated.