User manual

Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 52
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
2.5.4 MIO-at-a-Glance Table
Table 2-4 presents MIO information in a compact format for easy reference; the gray boxes represent
signals that are not usable in devices with CLG225 packages (7z010 dual core and 7z007s single core
devices). Refer to section PS-PL MIO-EMIO Signals and Interfaces for background information. This
section also includes important pin assignment considerations.
Table 2-4: MIO-at-a-Glance
MIO Voltage Bank 0
Package Bank 500
MIO Voltage Bank 1 Package Bank 501
0 1 2 3 4 5 6 7 8 9
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
Pins not available in
7z010 and 7z007s CLG225 devices
Pins not available in
7z010 and 7z007s
CLG225 devices
BOOT_MODE
The 20k ohm Boot Mode
pull-up/down resistors
are sampled at Reset.
Ethernet 0 Ethernet 1
MDIO
Device pll V
tx
ck
tx data
tx
ctl
rx
ck
rx data
rx
ctl
tx
ck
tx data
tx
ctl
rx
ck
rx data
rx
ctl
ck d
Quad SPI 0 Quad SPI 1
USB 0 USB 1
cs
1
cs
0
io
0
io
1
io
2
io
3
s
clk
fb
ck
s
clk
io
0
io
1
io
2
io
3
da
ta
dir
st
p
nx
t
data ck data
da
ta
dir
st
p
nx
t
data ck data
SPI
1, 0
SPI 1SPI 0SPI 1SPI 0SPI 1SPI 0SPI 1
mo
si
mi
so
ck
ss
0
ss
1
ss
2
ck
mi
so
ss
0
ss
1
ss
2
mo
si
mo
si
mi
so
ck
ss
0
ss
1
ss
2
ck
mi
so
ss
0
ss
1
ss
2
mo
si
mo
si
mi
so
ck
ss
0
ss
1
ss
2
ck
mi
so
ss
0
ss
1
ss
2
mo
si
mo
si
mi
so
ck
ss
0
ss
1
ss
2
SDIO
1, 0
SDIO 1SDIO 0SDIO 1SDIO 0SDIO 1SDIO 0SDIO 1
io
0
c
m
d
ck
io
1
io
2
io
3
ck
c
m
d
io
0
io
1
io
2
io
3
io
0
c
m
d
ck
io
1
io
2
io
3
ck
c
m
d
io
0
io
1
io
2
io
3
io
0
c
m
d
ck
io
1
io
2
io
3
ck
c
m
d
io
0
io
1
io
2
io
3
io
0
c
m
d
ck
io
1
io
2
io
3
SD Card Detect and Write Protect are available in any of the shaded positions in any combination of the four signals.
0 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
SD Card Power Controls are available on an odd/even pin basis that corresponds to SDIO controllers 0 and 1.
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SMC interface choice: NOR/SRAM or NAND Flash
cs
0
no
te
data oe bls data
da
ta
address [0:24]
NOR/SRAM
MIO Pin 1 is optional:
addr 25, cs 1 or gpio
cs alewe
io
2
io
0
io
1
cle rd io 4 ~ 7
io
3
bu
sy
io 8 ~ 15
NAND Flash
0 1 2 3 4 5 6 7 8 9
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
CAN
0 rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx
1
tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx
CAN External Clocks are optionally available on any pin in any combination
UART
0
rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx
1
tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx
I2C
0
ck d ck d ck d ck d ck d ck d ck d ck d ck d ck d ck d
1
ck d ck d ck d ck d ck d ck d ck d ck d ck d ck d ck d
System
Timers
TTC 0
Clk In, Wave Out w ck w ck w ck
TTC 1
Clk In, Wave Out w ck w ck w ck
SWDT
Clk In, Reset Out ck r ck r ck r ck r ck r
GPIOs are available for each MIO pin. Pins 0 ~ 31 are controlled by GPIO bank 0. Pins 32 ~ 53 are controlled by GPIO bank 1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PJTAG Interface
t
di
t
do
t
ck
t
ms
t
di
t
do
t
ck
t
ms
t
di
t
do
t
ck
t
ms
t
di
t
do
t
ck
t
ms
ck ctl ck ctl
Clock and Control
Trace Port User Interface
8 9 10 11 12 13 14 15 2 3 0 1 4 5 6 7 2 3 0 1
Data