User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 520
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Example: Master Clock Port
1. Initiate a transmission of Sync and Announce frames at pre-defined intervals.
2. Initiate a transmission of PDelay_Req frames at regular intervals.
Example: Slave Clock Port
1. Initiate a transmission of PDelay_Req frames at regular intervals.
2. Wait for Sync frame for a predefined interval of time. If a Sync timeout occurs, change to become
a PTP master.
3. Wait for an Announce frame for a pre-defined interval of time. If an Announce timeout occurs,
change to become a PTP master.
If a PDelay_Req frame is not received for a predefined period of time, or no Pdelay_resp and
PDelay_resp_Follow_Up were received for a PDelay_Req packet, then there is a grave error. As part of
error handling, the whole PTP state machine can be stopped (for both PTP master and slave) and no
clock synchronization done (if it is a slave port).
The intervals as mandated by the protocol range from 2
-128
to 2
127
seconds. The interval is decided
by the system specification. Since the same timer is used for Sync, Announce and PDelay_Req frames,
the timer expiry duration is decided by the minimum time interval for all these frames.
In a typical use case, the Sync frames can be sent out every 125 milliseconds, Announce frames and
PDelay_Req frames every 1 second. Similarly, typical Announce frame timeouts can be 2-3 seconds
and PDelay_Req, PDelay_Resp, PDelay_Resp_Follow_up timeouts can be 3-5 seconds.
16.4.3 Best Master Clock Algorithm (BMCA)
The BMCA performs a distributed selection of the best candidate clock (which becomes the
grandmaster clock) based on different clock properties for the available clocks in the network:
•Priority1
• Clock class
• Clock accuracy
• Clock variance (offset scaled log variance)
•Priority2
• Clock identity (to break the tie)
Refer to the IEEE 1588 Standard Specification for more information on clock attributes and BMCA.
In a typical implementation, each clock port can be identified with a structure which has fields for the
above clock properties. Other than these properties, the BMCA clock port can also be identified with
the steps removed field. For more information regarding this field refer to the IEEE1588
specifications. When a slave receives Announce frames from multiple master hosts, the steps removed
field can become significant in deciding the master clock.
The implementation should maintain an identical structure to identify the current grandmaster clock
properties. The BMCA is invoked when an Announce frame is received by the slave.