User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 521
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
Example: BMCA
1. Compare the fields of the Announce frame received with that of the current grandmaster starting
with Priority1, progressing to the next field in the event of a tie.
2. The one with a higher priority becomes the new grandmaster.
16.4.4 PTP Packet Handling at the Master
Refer to IEEE 1588 Standard Specification for more information on packet formats and protocol.
1. Form and send Sync frames at regular intervals. For two-step clocks (as in the Zynq-7000
AP SoC) the originTimestamp field should be zero. The sequenceId should be 1 greater than the
sequenceId of the last Sync frame transmitted from the same master port. Refer to section
16.4.1 Overview for some examples on setting header fields.
2. Read and store exact time stamp for the transmitted Sync frame. The Controller generates an
interrupt on successful transmission of a Sync frame. The registers gem.ptp_tx_s and
gem.ptp_tx_ns are read and stored to represent the exact time stamp for the transmitted Sync
frame in the interrupt handler.
3. Form and send the Follow_Up frame immediately after the successful transmission of the
Sync frame. The sequenceId should be the same as that of the just transmitted Sync frame. The
10 byte preciseOriginTimestamp field should be created using the stored seconds and
nanoseconds timestamp for the Sync frame. The Follow_Up frame is transmitted and since it is
not an event message, it is not time stamped by the hardware.
Note: The clock time stamp point for the AP SoC’s GigE is the MII interface. Since the Sync frame
travels through the external PHY after this time stamp point, the hardware observed time stamp
does not take care of the delay introduced by the external PHY. Users should determine the
typical external PHY latencies for their systems and add the same to the preciseOriginTimestamp
field.
4. Form and send Announce frames at regular intervals. The Announce frame should be set with
the clock attributes for the PTP master clock. The Announce frame is transmitted and since it is
not an event message, it is not time stamped by the hardware.
5. Send PDelay_Req frames at regular intervals. The master, acting as a peer for the PDelay
measurement state machine must send PDelay_Req frames at regular intervals. The sequenceId
field is assigned with a value of 1 greater than the last sent PDelay_Req frame. The field
originTimestamp can typically be filled up with a zero value along with the reserved field.
6. Read and store the exact time stamp for the transmitted PDelay_Req frame. The controller
generates an interrupt on successful transmission of the PDelay_Req frame. The registers
gem.ptp_peer_tx_s and gem.ptp_peer_tx_ns are read and stored to represent the time stamp of
the transmitted PDelay_Req frame in the interrupt handler. Let this time stamp be t1.
Note: Since the clock time stamp point is the MII interface and the PDelay_Req frame travels
through the external PHY after this point, the exact time stamp should be created by adding the
introduced delays by the external PHY.
7. Store the time stamp for the received PDelay_Resp frame. The Master receives a PDelay_Resp
frame from the peer clock. The controller generates a PDelay_Resp received interrupt. The master
reads the registers gem.ptp_peer_rx_s and gem.ptp_peer_rx_ns registers and stores them as the
received timestamp for the PDelay_Resp frame. Let this timestamp be t4.