User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 524
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
16.5.2 Status and Statistics Registers
The statistics registers hold counts for various types of events associated with transmit and receive
operations. These registers, along with the status words stored in the receive buffer list, enable
software to generate network management statistics compatible with IEEE 802.3. (See Table 16-10).
Table 16-9: Ethernet Control Register Overview
Function Register Name Description
MAC Configuration
net_{cfg,ctrl,status}
tx_pauseq
rx_pauseq
tx_pfc_pause
ipg_stretch
stacked_vlan
Network control, configuration and status.
Rx, Tx Pause clocks.
IPG stretch.
DMA Unit
tx_status
rx_status
tx_qbar
rx_qbar
dma_cfg
Control.
Receive, Transmit Status.
Receive, Transmit Queue Base Address Control.
Interrupts
intr_{status,en,dis, mask} Interrupt status, enable/disable, and mask
intr_dis_pq{1:7}
intr_en_pq{1:7}
intr_mask_pq{1:7}
wake_on_lan
isr_pq{1:7}
PHY Maintenance phy_maint PHY maintenance
MAC Address
Filtering and ID
Match
hash_{top,bot}
spec_addr{1:4}_{bot,top}
spec_addr1_mask_{bot,top}
type_id_match{1:4}
Hash address, Specific {4:1} addresses High/Low.
Match Type.
IEEE 1588 –
Precision Time
Protocol
timer_{s,ns}
timer_{adjust,incr}
timer_strobe_{s,ns}
IEEE 1588 second, nanosecond counter and
adjustment, increment.
ptp_tx_{s,ns}
ptp_peer_tx_{s,ns}
IEEE 1588 Tx normal/peer second, nanosecond
counter.
ptp_rx_{s,ns}
ptp_peer_rx_{s,ns}
IEEE 1588 Rx normal/peer second, nanosecond
counter.
Clocks and Reset
slcr.GEM{1,0}_CLK_CTRL
slcr.GEM{1,0}_RCLK_CTRL
slcr.GEM{1,0}_CPU_1XCLKACT
slcr.GEM_RST_CTRL
Refer to Chapter 25, Clocks and Chapter 26, Reset
System for more information.
I/O Signal Routing
slcr.MIO_PIN_{xxx} Refer to IOP Interface Connections, page 48 for MIO
pin programming information.