User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 530
UG585 (v1.11) September 27, 2016
Chapter 16: Gigabit Ethernet Controller
16.6.7 MIO Pin Considerations
LVCMOS33 is not supported for the RGMII interface. Recommendation is to use 1.8/2.5V I/O
standards.
16.7 Known Issues
1. On TX, GigE needs multiple descriptors with the last descriptor in the BD ring having the used bit
set. It is needed to ensure the GigE does not wrap and attempt to transmit the same frames more
than once.
On RX, there is no hard requirement to have multiple buffer descriptors, although it is a very
sensible thing to minimize the chance of getting buffer resource errors (where the hardware has
a frame to write to memory, but there is no free buffer(s) to write to). Extreme overflow
conditions in general are more likely when these buffer resource errors occur.
Workaround: Configure at least two buffer descriptors for both Tx/Rx data paths.
2. It is possible to have the last frame(s) stuck in the RX FIFO with the software having no way to get
the last frame(s) out of there. The GEM only initiates a descriptor request when it receives
another frame. Therefore, when a frame is in the FIFO and a descriptor only becomes available at
a later time and no new frames arrive, there is no way to get that frame out or even know that it
exists.
This issue does not occur under typical operating conditions. Typical operating conditions are
when the system always has incoming Ethernet frames. The above mentioned issue occurs when
the MAC stops receiving the Ethernet frames.
Workaround: There is no workaround in the software.
3. When discarding a frame or detecting an error, the GEM stores a status packet in the receive FIFO
(write side) indicating the erroneous condition. Once that status packet reaches the front of the
FIFO (read side) the error counter is incremented. When the FIFO is full no additional status
packets can be written into the FIFO and any further errors are discarded. For example, there
could be thousands of overflow errors but the overflow error counter only registers the first few.
This problem applies to all errors for which stats are maintained.
As a secondary problem the errors are only visible once they reach the front of the FIFO. If there
is a packet at the beginning of the FIFO that cannot be written to memory because of
unavailability of a RX DMA descriptor, many errors could occur that are not visible to software.
The error counters stay at zero because all the error status packets are backed up behind the data
packet.
Workaround: There is no workaround in the software.
4. GigE has an issue with the Rx packet buffer DMA design. The issue occurs under extreme Rx
traffic conditions with not enough DMA bandwidth. This results in the Rx packet buffer filling up,
leading to an overflow. The packet buffer overflow causes an overflow status word to be written
into the packet buffer for reporting. If the extreme traffic condition persists for a long time, this
results in a large number of such overflow status words being written into the packet buffer. This