User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 538
UG585 (v1.11) September 27, 2016
Chapter 17: SPI Controller
Manual SS
Software selects the manual slave select method by setting the spi.Config_reg0 [Manual_CS] bit = 1.
In this mode, software must explicitly control the slave select assertion/de-assertion. When the
[Manual_CS] bit = 0, the controller hardware automatically asserts the slave select during a data
transfer.
Automatic SS
Software selects the auto slave select method by programming the spi.Config_reg0 [Manual_CS] bit
= 0. The SPI controller asserts/de-asserts the slave select for each transfer of TxFIFO content on to
the MOSI signal. Software writes data to the TxFIFO and the controller asserts the slave select
automatically, transmits the data in the TxFIFO and then de-asserts the slave select. The slave select
gets de-asserted after all the data in the Tx FIFO is transmitted. This is the end of the transfer.
Software ensures the following in automatic slave select mode.
• Software continuously fills the TxFIFO with the data bytes to be transmitted, without the TxFIFO
becoming empty, to maintain an asserted slave select.
• Software continuously reads data bytes received in the RxFIFO to avoid overflow.
Software uses the TxFIFO and RxFIFO threshold levels to avoid FIFO under- and over-flows. The
TxFIFO Not Full condition is flagged when the number of bytes in TxFIFO is less than the TxFIFO
threshold level. The RxFIFO full condition is flagged when the number of bytes in RxFIFO is equal to
128.
Manual Start
Enable
Software selects the manual transfer method by setting the spi.Config_reg0 [Man_start_en] bit = 1.
In this mode, software must explicitly start the data transfer using manual start command
mechanism. When the [Man_start_en] bit = 0, the controller hardware automatically starts the data
transfer when there is data available in the TxFIFO.
Auto SS
(controller)
Manual Start 0 1
Controller hardware controls the slave select, but
the software must issue the start command to
serialize data in the TxFIFO. This mode is applicable
for specific use cases such as sending small chunks
of data that fit into the SPI controller FIFO.
Auto Start 00
Controller hardware controls the slave select and
serializes data when there is data in the TxFIFO.
Table 17-1: SPI Master Mode SS and Start Modes (Cont’d)
Slave Select
Control
Data Transfer
Start Control
Manual
Slave
Select
Manual Start
Enable &
Command
Operation