User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 539
UG585 (v1.11) September 27, 2016
Chapter 17: SPI Controller
Command
Software starts a manual transfer by writing a 1 to the spi.Config_reg0 [Man_start_com] bit. When
the software writes the 1, the controller hardware starts the data transfer and transfers all the data
bytes present in the TxFIFO. The [Man_start_com] bit is self-clearing. Writing a 1 to this bit is ignored
if [Man_start_en] = 0. Writing a 0 to [Man_start_com] has no effect, regardless of mode.
17.2.2 Multi-Master Capability
For Multi-master mode, the controller is programmed for master mode [MODE_SEL] and can initiate
transfers on any of the slave selects. When the software is ready to initiate a transfer, it enables the
controller using the [SPI_EN] bit. When the transaction is done, the software disables the controller.
The controller cannot be selected by an external master when the controller is in Master Mode.
The controller detects another master on the bus by monitoring the open-drain slave select signal
(active Low). The detection mechanism is enabled by the [Modefail_gen_en]. When the controller
detects another master, it sets the spi.Intr_status_reg0 [MODE_FAIL] interrupt status bit and clears
the spi.En_reg0 [SPI_EN] control bit. The software can receive the [MODE_FAIL] interrupt so it can
abort the transfer, reset the controller, and re-send the transfer.
17.2.3 Slave Mode
In slave mode, the controller receives messages from the external master and outputs a simultaneous
reply. The controller enters slave mode when spi.Config_reg0 [MODE_SEL] = 0 and spi.En_reg0
[SPI_EN] = 1.
The SCLK latches data on the MOSI input. If the slave select input signal is High (inactive), the
controller ignores the MOSI input. When the slave select is asserted, it must be held active for the
duration of the transfer. If SS de-asserts during the transfer, the controller sets the
spi.Intr_status_reg0 [MODE_FAIL] interrupt bit. The software receives the [MODE_FAIL] interrupt so it
can abort the transfer, reset the controller, and re-send the transfer.
The error mechanism is enabled by the [Modefail_gen_en] bit.
Data to be sent to the master is written into the TxFIFO by software and then serialized onto the
master input (MISO) signal by the controller. Transmission continues while there is still data in the
TxFIFO and the slave select signal remains asserted (active Low).
Clocking
The slave select input pin must be driven synchronously to the SCLK input. The controller operates in
the SPI_Ref_Clk clock domain. The input signals are synchronized and analyzed in the SPI_Ref_Clk
domain.
Word Detection
The start of a word is detected in th SPI_Ref_Clk clock domain.