User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 543
UG585 (v1.11) September 27, 2016
Chapter 17: SPI Controller
• Set Mode fail generation, [Modefail_gen_en], for multi-master mode systems.
•Set SS to 0b1111 to de-assert all the slave selects before the start of transfers.
Example: SPI 0 Configuration for Master Mode
This example uses a single chip select, a baud rate of 12.5 Mb/s, a clock phase set to inactive, and a
clock polarity of quiescent High.
1. Configure the controller: Write 0x0002_FC0F to the spi.Config_reg register.
a. De-assert all chip selects (for now): [CS] = 1111.
b. No external 3-to-8 chip select decoder. [PERI_SEL] = 0.
c. Set baud rate to 12.5 Mbps. [BAUD_RATE_DIV] = 1.
This example assumes a 50 MHz SPI_Ref_Clk. Baud rate generator description is in section
17.3.3 Master Mode Data Transfer.
d. Set clock phase, [CLK_PH] and Polarity, [CLK_POL] to 1. These parameters are discussed in
section 17.5.1 Protocol.
e. Select Master mode: [MODE_SEL] = 1.
f. Look for bus collisions: [Modefail_gen_en] = 1.
g. Do not initiate a transmission. [Man_start_com] = 0.
17.3.3 Master Mode Data Transfer
The four combinations of master operating mode are described in section 17.2.1 Master Mode. The
examples below illustrate the programming steps for each mode.
Example: Master Mode – Manual SS and Manual Start
1. Enable manual SS: Write 1 to spi.Config_reg [Manual_CS].
2. Select manual start: Write 1 to spi.Config_reg [Man_start_en].
3. Assert slave select: Set spi.Config_reg [CS] = 1101 to assert slave select 1.
4. Enable the controller: Write 1 to spi.EN_reg0 [SPI_EN].
5. Write bytes to the TxFIFO:
a. Write the data to the TxFIFO using the register spi.Tx_data_reg.
b. Continue to write data to the TxFIFO to its full depth or until no further data is needed to be
written.
c. Increment the data byte counter in the driver software after each byte is written to the
TxFIFO.
6. Enable the interrupts: Write 0x27 to spi.Intrpt_en_reg to enableRxFIFO full, RxFIFO overflow,
TXFIFO empty, and fault conditions.
7. Start the data transfer: Set spi.Config_reg0 [Man_start_com] = 1.
8. Wait for interrupts.