User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 545
UG585 (v1.11) September 27, 2016
Chapter 17: SPI Controller
6. Enable the interrupts: Write 0x27 to spi.Intrpt_en_reg to enable RxFIFO full, RxFIFO overflow,
TxFIFO empty, and fault conditions.
7. Start the data transfer: Set spi.Config_reg0 [Man_start_com] = 1.
8. Interrupt handler: Transfer any additional data to the slave the required data to SPI slave using
the interrupt handler.
9. Disable interrupts: Write 0x27 to the spi.Intrpt_dis_reg to disable RxFIFO full, RxFIFO overlflow,
TxFIFO empty, and fault conditions.
10. Disable the controller: Set spi.En_reg0 [SPI_EN] = 0.
11. De-assert slave select: Set spi.Config_reg0 [CS] = 1111.
17.3.4 Slave Mode Data Transfer
Example: Slave Mode - Interrupt Driven
Ensure that the controller configuration is done and then:
1. Slave configuration: Write 0 to spi_Config_reg0.
2. Enable the interrupts: Write 0x37 to spi.Intrpt_en_reg to enable RxFIFO Not empty, RxFIFO full,
RxFIFO overflow, TxFIFO empty, and fault conditions.
3. Enable the controller: Write 1 to spi.En_reg [SPI_EN].
4. Interrupt Handler: Receive data from master using the interrupt handler.
5. Disable the interrupts: Write 0x37 to spi.Intrpt_DIS_reg to disable RxFIFO Not empty, RxFIFO
full, RxFIFO overflow, TxFIFO empty, and fault conditions.
6. Disable the controller: Write 0 to spi_En_reg0 [SPI_EN].
17.3.5 Interrupt Service Routine
Example: Interrupt Service Routine
This example handles RxFIFO overflow/underflow, multi-master collision (mode fail) and handles Rx
and Tx data transfers.
1. Disable all interrupts except TxFIFO Full and RxFIFO Not Empty: Write 0x027 to
spi.Intr_dis_REG.
2. Determine the source of the interrupt: Read the interrupt status register spi.Intr_status_reg0.
3. Clear the interrupts: Write 1s to the interrupt status register spi.Intr_status_reg0.
4. Check for Mode fail Interrupt: (multi-master operation). On mode fail, abort the current
transfer:
a. Reset the controller
b. Re-configure the controller
c. Re-send the data.
5. Empty the RxFIFO: Read spi.Intr_status_reg0 [RX_FIFO_full] bits: